OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
166,089 Commits 31 Branches 0 Tags 2.2 GiB
Commit Graph

8 Commits

Author SHA1 Message Date
Tim Northover 40e9efd725 AArch64: add initial NEON support 
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
 2013-08-01 09:20:35 +00:00
Michael J. Spencer df1ecbd734 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 
llvm-svn: 182680
 2013-05-24 22:23:49 +00:00
David Majnemer 938493999e Fix undefined behavior in AArch64 
A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to
execute shifts that perform undefined behavior. Instead of attempting
to perform the 64-bit rotation, treat it as a no-op.

llvm-svn: 179317
 2013-04-11 20:13:52 +00:00
Tim Northover 5816ca117b AArch64: implement ETMv4 trace system registers. 
llvm-svn: 178637
 2013-04-03 12:31:29 +00:00
Tim Northover 08bb3ce383 AArch64: implement GICv3 system registers 
llvm-svn: 178236
 2013-03-28 14:30:46 +00:00
Tim Northover 91a51c5a7c Add icache prefetch operations to AArch64 
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

llvm-svn: 174495
 2013-02-06 09:04:56 +00:00
Tim Northover bcaca87d53 Fix formatting in AArch64 backend. 
This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

llvm-svn: 174370
 2013-02-05 13:24:56 +00:00
Tim Northover 969afbec64 Remove cyclic dependency in AArch64 libraries 
This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.

llvm-svn: 174369
 2013-02-05 13:24:47 +00:00