7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
36a3abc671
Add support for the R and Q constraints.
...
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
faff512536
Emitting ARM build attributes and values as ULEB, rather than char.
...
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
2aedba6c5e
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
...
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
61faa55b74
Separate MCInstPrinter registration from AsmPrinter registration.
...
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
...
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
204c128f66
Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
...
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
4af8647e17
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
...
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
dbfb29d6c0
Use ARMPseudoExpand for ARM tail calls.
...
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
2dfe8e3ccd
Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
...
TableGen'erated MC lowering pseudo-expansion.
llvm-svn: 134712
2011-07-08 18:15:12 +00:00
95dee40343
Use TableGen'erated pseudo lowering for ARM.
...
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
llvm-svn: 134705
2011-07-08 17:40:42 +00:00
148220306f
The VMLA instruction and its friends are not actually fused; they're plain old
...
multiply-accumulate instructions with separate rounding steps.
llvm-svn: 134609
2011-07-07 08:28:52 +00:00
ab37af9af3
createMCInstPrinter doesn't need TargetMachine anymore.
...
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
e9cc901814
Refact ARM Thumb1 tMOVr instruction family.
...
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
llvm-svn: 134204
2011-06-30 23:38:17 +00:00
b98ab91e39
Thumb1 register to register MOV instruction is predicable.
...
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
llvm-svn: 134197
2011-06-30 22:10:46 +00:00
353da73186
Pseudo-ize the t2LDMIA_RET instruction.
...
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.
llvm-svn: 134173
2011-06-30 18:25:42 +00:00
417671a7b1
Pseudo-ize the Thumb tPOP_RET instruction.
...
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.
llvm-svn: 134172
2011-06-30 17:34:04 +00:00
a8a8067dec
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
...
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
llvm-svn: 134114
2011-06-29 23:25:04 +00:00
d00e8ad803
Implement the 'M' output modifier for arm inline asm. This is fairly
...
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
llvm-svn: 132242
2011-05-28 01:40:44 +00:00
d23bfb8a7a
Make size computation less brittle.
...
llvm-svn: 132222
2011-05-27 22:05:41 +00:00
33a73c7755
Reorganize these slightly according to operand type.
...
llvm-svn: 132128
2011-05-26 18:22:26 +00:00
26ddb12118
Mark tBX as an indirect branch rather than a return.
...
llvm-svn: 132107
2011-05-26 03:41:12 +00:00
a946f476d3
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
...
llvm-svn: 132086
2011-05-25 21:53:50 +00:00
8c5e4192e6
Implement the 'm' modifier. Note that it only works for memory operands.
...
Part of rdar://9119939
llvm-svn: 132081
2011-05-25 20:51:58 +00:00
3088e0a179
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
...
fixes <rdar://problem/9495913>
llvm-svn: 132042
2011-05-25 04:45:27 +00:00
deaf994ff0
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
...
reflect their actual meaning and match the ARM instructions.
llvm-svn: 132039
2011-05-25 04:45:14 +00:00
1b724948e9
Implement the arm 'L' asm modifier.
...
Part of rdar://9119939
llvm-svn: 132024
2011-05-24 23:27:13 +00:00
b1dda56ac2
Implement the immediate part of the 'B' modifier.
...
Part of rdar://9119939
llvm-svn: 132023
2011-05-24 23:15:43 +00:00
d4562566b4
Add more unimplemented asm modifiers and some documentation of what they
...
do.
Part of rdar://9119939.
llvm-svn: 132015
2011-05-24 22:27:43 +00:00
7617883ce3
Add support for the arm 'y' asm modifier.
...
Fixes part of rdar://9444657
llvm-svn: 132011
2011-05-24 22:10:34 +00:00
bc90690b24
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
...
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
llvm-svn: 131894
2011-05-23 01:57:17 +00:00
652bfdb1ab
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
e90c1cb221
sets bit 0 of the function address of thumb function in .symtab
...
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
39ecf816c5
Do not emit location expression size twice.
...
llvm-svn: 130854
2011-05-04 19:00:57 +00:00
3e021533cd
Teach dwarf writer to handle complex address expression for .debug_loc entries.
...
This fixes clang generated blocks' variables' debug info.
Radar 9279956.
llvm-svn: 130373
2011-04-28 02:22:40 +00:00
e3745fdcf3
Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
...
llvm-svn: 130326
2011-04-27 20:29:27 +00:00
cae2fbd6fc
Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
...
llvm-svn: 130178
2011-04-26 00:12:46 +00:00
3c39ec2933
Add asserts.
...
llvm-svn: 129995
2011-04-22 16:44:29 +00:00
94ad6ac13c
Fix DWARF description of Q registers.
...
llvm-svn: 129952
2011-04-21 23:22:35 +00:00
3712c14be9
Fix DWARF description of S registers.
...
llvm-svn: 129947
2011-04-21 22:48:26 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
00f0cddfd4
We need to pass the TargetMachine object to the InstPrinter if we are printing
...
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
llvm-svn: 127986
2011-03-21 04:13:46 +00:00
3af6fe66b9
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
...
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
llvm-svn: 127637
2011-03-15 00:30:40 +00:00
3f2096eafe
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
...
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
llvm-svn: 127515
2011-03-12 00:45:26 +00:00
f026d9ed53
Pseudo-ize the ARM 'B' instruction.
...
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
6d371ce37e
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
692f633df9
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
...
llvm-svn: 127106
2011-03-05 18:44:00 +00:00
9e66cbb366
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
...
llvm-svn: 127105
2011-03-05 18:43:55 +00:00
a8d177b2d4
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
...
llvm-svn: 127104
2011-03-05 18:43:50 +00:00
51537f1c7f
Add unwind information emission for thumb stuff
...
llvm-svn: 127103
2011-03-05 18:43:43 +00:00
e7410dd0d5
Preliminary support for ARM frame save directives emission via MI flags.
...
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
llvm-svn: 127101
2011-03-05 18:43:32 +00:00
e84af17b6e
Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
...
llvm-svn: 126882
2011-03-02 21:20:09 +00:00
ec0fc7d842
Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
...
llvm-svn: 126689
2011-02-28 22:04:27 +00:00
e5ce4c9bcd
ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .o
...
llvm-svn: 125025
2011-02-07 19:07:11 +00:00
85b0af177f
Rework some .ARM.attribute work for improved gcc compatibility.
...
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.
llvm-svn: 124995
2011-02-07 00:49:53 +00:00
2f2435d026
Last round of fixes for movw + movt global address codegen.
...
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
llvm-svn: 123991
2011-01-21 18:55:51 +00:00
dfce83c8f5
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
...
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
llvm-svn: 123619
2011-01-17 08:03:18 +00:00
e9eae0f887
JimG sez: "The value-kinds look like masks, but they're not consistently used
...
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."
So I am reverting this bit until a more opportune time.
llvm-svn: 123340
2011-01-12 23:21:49 +00:00
9c5b65d289
1. Support ELF pcrel relocations for movw/movt:
...
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
2011-01-12 00:19:25 +00:00
e45d685895
Clean up ARM subtarget code by using Triple ADT.
...
llvm-svn: 123276
2011-01-11 21:46:47 +00:00
62acecd7e1
Model operand restrictions of mul-like instructions on ARMv5 via
...
earlyclobber stuff. This should fix PRs 2313 and 8157.
Unfortunately, no testcase, since it'd be dependent on register
assignments.
llvm-svn: 122663
2011-01-01 20:38:38 +00:00
429bb1e2cc
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
...
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
llvm-svn: 122131
2010-12-18 02:13:59 +00:00
a7dabbd2cf
Avoid report_fatal_error in ARM's PrintAsmOperand method.
...
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
llvm-svn: 122100
2010-12-17 23:06:42 +00:00
b5743b9d76
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
8c1fabe367
Refactor a bit for legibility.
...
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
96254146cf
Make sure to propagate the predicate operands for LEApcrel to ADR.
...
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
...
process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
6233189713
Add a textual message to the assert.
...
llvm-svn: 121349
2010-12-09 01:23:51 +00:00
ed40288eb4
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
...
referencing the stack pointer as they say they are.
llvm-svn: 121347
2010-12-09 01:22:19 +00:00
ce2bd8d05f
Add support for binary encoding of ARM 'adr' instructions referencing constant
...
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
llvm-svn: 120635
2010-12-02 00:28:45 +00:00
dc35e067c1
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
...
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
llvm-svn: 120594
2010-12-01 19:47:31 +00:00
d0d1329fc8
Move the ARMAsmPrinter class defintiion into a header file.
...
llvm-svn: 120551
2010-12-01 03:45:07 +00:00
3b4e2ab5f3
Pseudo-ize ARM MOVPCRX
...
llvm-svn: 120442
2010-11-30 18:56:36 +00:00
cd5e30f6c6
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
...
rdar://8685712
llvm-svn: 120438
2010-11-30 18:30:19 +00:00
8294a30d54
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
...
llvm-svn: 120371
2010-11-30 00:48:15 +00:00
7ec3d34553
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
...
instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
81af4f9eb1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
...
data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
58bc36a3a9
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
150b1ad7f8
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
...
llvm-svn: 120303
2010-11-29 18:37:44 +00:00
08c562bba6
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
...
in the MC lowering process.
llvm-svn: 119559
2010-11-17 21:05:55 +00:00
5cf10ea1d1
Add FIXMEs.
...
llvm-svn: 119167
2010-11-15 18:36:48 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
de16ca8ecc
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
...
llvm-svn: 119071
2010-11-14 21:00:02 +00:00
c5afd12557
even more simplifications. ARM MCInstLowering is now just
...
a single function instead of a class. It doesn't need the
complexity that X86 does.
llvm-svn: 119070
2010-11-14 20:58:38 +00:00
b28e691657
simplify and tidy up
...
llvm-svn: 119066
2010-11-14 20:31:06 +00:00
ca21cd749e
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
f23b2d9d8d
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
a942ad4222
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
2fd4c37d8b
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
38f8e76e51
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
0ef474730f
Revert 118422 in search of bot verdancy.
...
llvm-svn: 118429
2010-11-08 19:17:22 +00:00
f3e224f830
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
...
llvm-svn: 118422
2010-11-08 17:58:07 +00:00
5a2c68d308
MC'ize the '.code 16' and '.thumb_func' ARM directives.
...
llvm-svn: 118301
2010-11-05 22:08:08 +00:00
ff9e507d8e
MC'ize simple ARMConstantValue entry emission (with a FIXME).
...
llvm-svn: 118295
2010-11-05 20:34:24 +00:00
1df82e67d1
Add FIXME.
...
llvm-svn: 118280
2010-11-05 17:37:13 +00:00
4a0c2d73c3
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
e477b1ad30
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
752913d6ba
Add a virtual destructor.
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llvm-svn: 117280
2010-10-25 18:38:32 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
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llvm-svn: 117275
2010-10-25 17:50:35 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
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Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
25cd3bfbd7
remove trailing whitespace
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llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
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Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
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"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
8025f89860
target operand flag values aren't a bitmask
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llvm-svn: 115798
2010-10-06 16:51:55 +00:00
fae8305e2b
Nuke the rest of the :comment references
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llvm-svn: 115373
2010-10-01 23:21:38 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
c8e2e9d830
Nuke a few more unused asm strings
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llvm-svn: 115193
2010-09-30 19:53:58 +00:00
136ed51b08
80 column fix
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llvm-svn: 115149
2010-09-30 15:25:22 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
05eccf0e44
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
45c83d496f
Factor out dbg_value comment printing and teach MC asm printing to use it.
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This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
175d6411c8
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114915
2010-09-27 22:28:11 +00:00
9e9ed98305
ARM-mode eh.sjlj.longjmp MC lowering
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llvm-svn: 114896
2010-09-27 21:47:04 +00:00
11fed543c9
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114892
2010-09-27 21:28:44 +00:00
4a6ab13fb9
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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llvm-svn: 114758
2010-09-24 20:47:58 +00:00
c0aed7179a
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
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llvm-svn: 114707
2010-09-23 23:33:56 +00:00
7d34837676
never mind. I can't read, apparently
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llvm-svn: 114689
2010-09-23 19:42:17 +00:00
836341a17a
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
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constant. Hopefully the non-Darwin bots will like it...
llvm-svn: 114687
2010-09-23 19:32:40 +00:00
3d50a3e237
explicit 'unsigned long' on constant value. Hopefully make bots happier.
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llvm-svn: 114686
2010-09-23 19:08:04 +00:00
e38495dbc0
Unbreak build. Jim, please review.
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llvm-svn: 114684
2010-09-23 18:57:26 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
1f57cc4a59
add FIXME
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llvm-svn: 114578
2010-09-22 20:55:15 +00:00
284eebc1ae
Add MC instruction printer support for ARM and Thumb1 jump tables.
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llvm-svn: 114555
2010-09-22 17:39:48 +00:00
1573b29ea7
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
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llvm-svn: 114553
2010-09-22 17:15:35 +00:00
754e1efffc
Clean up comment.
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llvm-svn: 114550
2010-09-22 16:45:13 +00:00
d64f9b8381
Add start of support for MC instruction printer of ARM jump tables. Filling in
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the rest of it is next up.
llvm-svn: 114500
2010-09-21 23:28:16 +00:00
cbac342e1a
Fix errant printing of [v]ldm instructions that aren't a pop
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llvm-svn: 114445
2010-09-21 16:45:31 +00:00
af5d63583e
factor out a simple helper function to create a label for PC-relative
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instructions (PICADD, PICLDR, et.al.)
llvm-svn: 114243
2010-09-18 00:05:05 +00:00
3d97920829
Add MC-inst handling for tPICADD
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llvm-svn: 114237
2010-09-17 23:41:53 +00:00
7a6c37d3e7
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
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and shift instructions on ARM. Update the tests to match.
llvm-svn: 114230
2010-09-17 22:36:38 +00:00
132a0ce787
Hook up verbose asm comment printing for SOImm operands in MC printer
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llvm-svn: 114215
2010-09-17 21:33:25 +00:00
0d35df1cfe
handle the upper16/lower16 target operand flags on symbol references for MC
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instruction lowering.
llvm-svn: 114191
2010-09-17 18:25:25 +00:00
a7d430b51c
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
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llvm-svn: 114183
2010-09-17 16:25:52 +00:00
218e22da8b
MC-ization of the PICLDR pseudo. Next up, adding the other variants
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(PICLDRB, et. al.) and PICSTR*
llvm-svn: 114098
2010-09-16 17:43:25 +00:00
a625b0110b
Remove support for "dregpair" operand modifier, now that it is no longer being
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used for anything.
llvm-svn: 114067
2010-09-16 04:55:00 +00:00
Bill Wendling