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Author SHA1 Message Date
Chad Rosier b4ac423ed4 [arm fast-isel] Appease the machine verifier by using the proper register 
classes.  The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue().  Those will be
a little more challenging to cleanup.
rdar://12719844

llvm-svn: 168735
 2012-11-27 22:29:43 +00:00
Chad Rosier 0c00758065 [arm fast-isel] Appease the machine verifier by using the proper register 
classes.
rdar://12719844

llvm-svn: 168733
 2012-11-27 22:12:11 +00:00
Chad Rosier 2ec7db0968 [arm fast-isel] Appease the machine verifier by using the proper register 
classes.  Also a bit of cleanup.
rdar://12719844

llvm-svn: 168728
 2012-11-27 21:46:46 +00:00
Chad Rosier 2e82ad12a6 [arm fast-isel] Appease the machine verifier by using the proper register 
classes.  The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844

llvm-svn: 168657
 2012-11-27 01:06:49 +00:00
Chad Rosier 66bb178eef Revert r167620; this can be implemented using an existing CL option. 
llvm-svn: 167622
 2012-11-09 18:25:27 +00:00
Chad Rosier 332fc75b2c Add support for -mstrict-align compiler option for ARM targets. 
rdar://12340498

llvm-svn: 167620
 2012-11-09 17:29:38 +00:00
Chad Rosier 65710a7589 [arm fast-isel] Appease the machine verifier by using the proper register 
classes.  For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152

llvm-svn: 167508
 2012-11-07 00:13:01 +00:00
Bill Wendling 12cda50f1f When a block ends in an indirect branch, add its successors to the machine basic block. 
The CFG of the machine function needs to know that the targets of the indirect
branch are successors to the indirect branch.
<rdar://problem/12529625>

llvm-svn: 166448
 2012-10-22 23:30:04 +00:00
Bill Wendling 8ccd6ca199 Use the attribute enums to query if a parameter has an attribute. 
llvm-svn: 165550
 2012-10-09 21:38:14 +00:00
Micah Villmow cdfe20b97f Move TargetData to DataLayout. 
llvm-svn: 165402
 2012-10-08 16:38:25 +00:00
Bill Wendling 8baa61d85d Add methods which query for the specific attribute instead of using the 
enums. This allows for better encapsulation of the Attributes class.

llvm-svn: 165132
 2012-10-03 17:54:26 +00:00
Sylvestre Ledru 91ce36c986 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
llvm-svn: 164768
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru 721cffd53a Fix a typo 'iff' => 'if' 
llvm-svn: 164767
 2012-09-27 09:59:43 +00:00
Jush Lu 47172a064f [arm-fast-isel] Add support for ELF PIC. 
This is a preliminary step towards ELF support; currently ARMFastISel hasn't
been used for ELF object files yet.

llvm-svn: 164759
 2012-09-27 05:21:41 +00:00
Chad Rosier 8bf01fc663 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for 
non-aligned i32 loads/stores.
rdar://12304911

llvm-svn: 164381
 2012-09-21 16:58:35 +00:00
Chad Rosier 2364f58326 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for 
non-halfword-aligned i16 loads/stores.
rdar://12304911

llvm-svn: 164345
 2012-09-21 00:41:42 +00:00
Nadav Rotem a8e15b0892 Fix a few old-GCC warnings. No functional change. 
llvm-svn: 163309
 2012-09-06 11:13:55 +00:00
Jush Lu e87e559e62 [arm-fast-isel] Add support for ARM PIC. 
llvm-svn: 162823
 2012-08-29 02:41:21 +00:00
Jakob Stoklund Olesen e6afde59db Fix call instruction operands in ARMFastISel. 
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

llvm-svn: 162593
 2012-08-24 20:52:46 +00:00
Craig Topper fd1c925946 Remove virtual from many methods. These methods replace methods in the base class, but the base class methods aren't virtual so it just increased call overhead. 
llvm-svn: 162178
 2012-08-18 21:38:45 +00:00
Jush Lu 26088cb30e [arm-fast-isel] Add support for fastcc. 
Without fastcc support, the caller just falls through to CallingConv::C
for fastcc, but callee still uses fastcc, this inconsistency of calling
convention is a problem, and fastcc support can fix it.

llvm-svn: 162013
 2012-08-16 05:15:53 +00:00
Bob Wilson 3e6fa462f3 Fall back to selection DAG isel for calls to builtin functions. 
Fast isel doesn't currently have support for translating builtin function
calls to target instructions.  For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization.  Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel.  <rdar://problem/12008746>

llvm-svn: 161232
 2012-08-03 04:06:28 +00:00
Jush Lu 4705da9020 [arm-fast-isel] Add support for shl, lshr, and ashr. 
llvm-svn: 161230
 2012-08-03 02:37:48 +00:00
Eric Christopher b3322364e4 Add support for the ARM GHC calling convention, this patch was in 3.0, 
but somehow managed to be dropped later.

Patch by Karel Gardas.

llvm-svn: 161226
 2012-08-03 00:05:53 +00:00
Jush Lu e67e07b901 [arm-fast-isel] Add support for vararg function calls. 
llvm-svn: 160500
 2012-07-19 09:49:00 +00:00
NAKAMURA Takumi 0246724cd6 Revert r159804, "[arm-fast-isel] Add support for vararg function calls." 
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts.

llvm-svn: 159817
 2012-07-06 11:12:44 +00:00
Jush Lu 5e6e6264f4 [arm-fast-isel] Add support for vararg function calls. 
llvm-svn: 159804
 2012-07-06 03:02:37 +00:00
Jush Lu ac96b764ea Cleanup whitespace. 
llvm-svn: 158443
 2012-06-14 06:08:19 +00:00
Chad Rosier c6916f88a8 [arm-fast-isel] Add support for -arm-long-calls. 
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 158368
 2012-06-12 19:25:13 +00:00
Bill Wendling 4b79647a6e Re-enable the CMN instruction. 
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>

llvm-svn: 158302
 2012-06-11 08:07:26 +00:00
Chad Rosier f319324082 [arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0 
then DestReg is undefined.

llvm-svn: 157840
 2012-06-01 21:12:31 +00:00
Chad Rosier 820d248c4d [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic. 
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157696
 2012-05-30 17:23:22 +00:00
Chad Rosier 223faf719c [arm-fast-isel] Add support for non-global callee. 
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157336
 2012-05-23 18:38:57 +00:00
Chad Rosier aa9cb9df59 [fast-isel] Add support for selecting @llvm.trap(). 
llvm-svn: 156646
 2012-05-11 21:33:49 +00:00
Chad Rosier 3268692aa8 [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup. 
llvm-svn: 156632
 2012-05-11 19:40:25 +00:00
Chad Rosier 90f9afe659 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg 
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

llvm-svn: 156628
 2012-05-11 18:51:55 +00:00
Chad Rosier 519b12f927 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back 
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

llvm-svn: 156622
 2012-05-11 17:41:06 +00:00
Chad Rosier 466d3d8faa The return type is an unsigned, not a bool. 
llvm-svn: 156621
 2012-05-11 16:41:38 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
llvm-svn: 155188
 2012-04-20 07:30:17 +00:00
Jim Grosbach 0c509fa6bf Tidy up. 80 columns. 
llvm-svn: 154226
 2012-04-06 23:43:50 +00:00
Jakob Stoklund Olesen 6a2e99a46a Deduplicate ARM call-related instructions. 
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.

llvm-svn: 154144
 2012-04-06 00:04:58 +00:00
Craig Topper f6e7e12f75 Remove unnecessary llvm:: qualifications 
llvm-svn: 153500
 2012-03-27 07:21:54 +00:00
Craig Topper 5fa0caafc0 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h 
llvm-svn: 153422
 2012-03-26 00:45:15 +00:00
Bill Wendling 23f8c4a50c Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>

llvm-svn: 152959
 2012-03-16 23:11:07 +00:00
Chad Rosier 26d05887d9 [fast-isel] Address Eli's comments for r152847. Specifically, add a test case 
and still allow immediate encoding, just not with cmn.
rdar://11038907

llvm-svn: 152869
 2012-03-15 22:54:20 +00:00
Chad Rosier 01cecbffd6 [fast-isel] Don't try to encode LONG_MIN using cmn instructions. 
rdar://11038907

llvm-svn: 152847
 2012-03-15 21:40:23 +00:00
Chad Rosier 377f1f2d39 [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point 
condition flags to CPSR.  This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.

llvm-svn: 152243
 2012-03-07 20:59:26 +00:00
Lang Hames 718cfbe05a Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
 2012-03-06 00:19:55 +00:00
Jim Grosbach 6990e5f08c ARM use the right opcode for FP<->Integer move in fast-isel. 
rdar://10965031

llvm-svn: 151850
 2012-03-01 22:47:09 +00:00
Jakob Stoklund Olesen fa7a53746c Switch ARM target to register masks. 
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.

This patch does cause some assembly changes.  Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected.  MachineCopyPropagation may sometimes
leave a dead copy behind.

llvm-svn: 151331
 2012-02-24 01:19:29 +00:00
Craig Topper 760b134ffa Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. 
llvm-svn: 151134
 2012-02-22 05:59:10 +00:00
Chad Rosier fcd29ae390 [fast-isel] Add support for returning non-legal types with no sign- or zero- 
entend flag.

llvm-svn: 150774
 2012-02-17 01:21:28 +00:00
Chad Rosier a0d3c75015 Remove unnecessary assignment to temporary, ResultReg. 
llvm-svn: 150737
 2012-02-16 22:45:33 +00:00
Chad Rosier 0bc5132457 Add braces to if clause to make symmetric with associate else clause. 
llvm-svn: 150591
 2012-02-15 17:36:21 +00:00
Chad Rosier dccc4794e6 Use a temporary variable, rather then a series of redundant calls. 
llvm-svn: 150536
 2012-02-15 00:23:55 +00:00
Chad Rosier 5b9c3974d2 Remove unnecessary assignment to temporary, ResultReg. 
llvm-svn: 150520
 2012-02-14 22:29:48 +00:00
Chad Rosier 0ee8c513f7 [fast-isel] Add support for SUBs with non-legal types. 
llvm-svn: 150047
 2012-02-08 02:45:44 +00:00
Chad Rosier bd471255a9 [fast-isel] Add support for ORs with non-legal types. 
llvm-svn: 150045
 2012-02-08 02:29:21 +00:00
Chad Rosier ded4c99f2e [fast-isel] Add support for indirect branches. 
llvm-svn: 150014
 2012-02-07 23:56:08 +00:00
Craig Topper e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Chad Rosier 685b20c114 [fast-isel] Add support for ADDs with non-legal types. 
llvm-svn: 149934
 2012-02-06 23:50:07 +00:00
Duncan Sands ae22c60f90 Persuade GCC that there is nothing worth warning about here (there isn't). 
llvm-svn: 149834
 2012-02-05 14:20:11 +00:00
Chad Rosier b84a4b4c64 [fast-isel] Add support for URem. 
llvm-svn: 149716
 2012-02-03 21:23:45 +00:00
Chad Rosier e023d5d7f3 [fast-isel] Rename isZExt to isSigned. No functional change intended. 
llvm-svn: 149714
 2012-02-03 21:14:11 +00:00
Chad Rosier aaa55a88b6 [fast-isel] Add support for UDIV. 
llvm-svn: 149712
 2012-02-03 21:07:27 +00:00
Chad Rosier 41f0e78b6c [fast-isel] Add support for FPToUI. Also add test cases for FPToSI. 
llvm-svn: 149706
 2012-02-03 20:27:51 +00:00
Chad Rosier a8a8ac5d47 [fast-isel] Add support for selecting UIToFP. 
llvm-svn: 149704
 2012-02-03 19:42:52 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Eric Christopher d284c1d80d Fix assert. 
llvm-svn: 147966
 2012-01-11 20:55:27 +00:00
Jakob Stoklund Olesen 083dbdca7f Match SelectionDAG logic for enabling movt. 
Darwin doesn't do static, and ELF targets only support static.

llvm-svn: 147740
 2012-01-07 20:49:15 +00:00
Jakob Stoklund Olesen 8cdce7e690 Use getRegForValue() to materialize the address of ARM globals. 
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.

<rdar://problem/10658692>

llvm-svn: 147720
 2012-01-07 04:07:22 +00:00
Jakob Stoklund Olesen 68f034ee1a Use movw+movt in ARMFastISel::ARMMaterializeGV. 
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.

This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.

<rdar://problem/10629774>

llvm-svn: 147712
 2012-01-07 01:47:05 +00:00
Evan Cheng 68132d8093 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Chad Rosier ded6160473 VFP2 is required for FP loads. Noticed by inspection. 
llvm-svn: 146569
 2011-12-14 17:55:03 +00:00
Chad Rosier fce28914ea Tidy up. 
llvm-svn: 146568
 2011-12-14 17:32:02 +00:00
Chad Rosier a26979be29 Fix 80-column violation and extraneous brackets. 
llvm-svn: 146566
 2011-12-14 17:26:05 +00:00
Evan Cheng 7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
 2011-12-14 02:11:42 +00:00
Chad Rosier 563de603f7 [fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular 
load and then move the result from a GPR to a FPR.

llvm-svn: 146502
 2011-12-13 19:22:14 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
Chad Rosier c77830d21e [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Bob Wilson 80381f6cbf Fix 80-column issues. 
llvm-svn: 145783
 2011-12-04 00:52:23 +00:00
Chad Rosier ec3b77e00d [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Chad Rosier 9fd0e55e91 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Duncan Sands 12330650f8 Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
 2011-11-28 10:31:27 +00:00
Chad Rosier ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
llvm-svn: 144959
 2011-11-18 01:17:34 +00:00
Chad Rosier 0eff3e5c21 Add TODO comment. 
llvm-svn: 144920
 2011-11-17 21:46:13 +00:00
Chad Rosier 15b2498e88 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Chad Rosier ce619ddfc5 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Chad Rosier 80979b6ea6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Chad Rosier af13d767a2 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jay Foad 0745e645e0 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Chad Rosier 057b6d3476 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Chad Rosier ab7223e99a Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier 45110fdf8d Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Chad Rosier adfd200bcb Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Chad Rosier 2a1df883d0 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Chad Rosier 1198d894d0 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier a476e391f1 Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier 5196efdf36 Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00