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77 Commits

Author SHA1 Message Date
Craig Topper 399e39e0de Set displacementSize to 1 for instrucitons with mod==0x1. Fixes PR17310. Modified from patch by James Courtier-Dutton. 
llvm-svn: 200100
 2014-01-25 22:48:43 +00:00
David Woodhouse b33c2ef215 [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
llvm-svn: 199804
 2014-01-22 15:08:21 +00:00
David Woodhouse 2ef8d9c05c [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
llvm-svn: 199803
 2014-01-22 15:08:08 +00:00
David Woodhouse 9c74fdb8b9 [x86] Fix 16-bit disassembly of JCXZ/JECXZ 
llvm-svn: 199653
 2014-01-20 12:02:48 +00:00
David Woodhouse 5cf4c6750d [x86] Fix 16-bit handling of OpSize bit 
When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.

llvm-svn: 199650
 2014-01-20 12:02:35 +00:00
Craig Topper 5a44496988 VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions don't use the size fields it controls. 
llvm-svn: 199470
 2014-01-17 07:11:45 +00:00
Craig Topper 9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Craig Topper 623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper b771ffaf4c Remove old comment referring to an argument that no longer exists. 
llvm-svn: 198263
 2013-12-31 15:29:14 +00:00
Craig Topper 0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00
Elena Demikhovsky 371e363833 AVX-512: decoder for AVX-512, made by Alexey Bader. 
llvm-svn: 198013
 2013-12-25 11:40:51 +00:00
David Majnemer 64582671af X86 Disassembler: remove unused bool typedef-name 
llvm-svn: 194062
 2013-11-05 10:34:42 +00:00
Craig Topper 9eb8837ffa Replace C++ style comment with a C style comment to satisfy some of the build bots. 
llvm-svn: 191880
 2013-10-03 06:29:59 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Craig Topper 766c934814 Remove 0 as a valid encoding for the m-mmmm field. 
llvm-svn: 191732
 2013-10-01 07:10:28 +00:00
Craig Topper 8b278c5dc4 Remove unneeded fields from disassembler internal instruction format. 
llvm-svn: 191731
 2013-10-01 06:56:57 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes. 
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
 2013-09-30 02:46:36 +00:00
Richard Mitton 79917a913e Build fix 
llvm-svn: 189699
 2013-08-30 21:32:42 +00:00
Richard Mitton 576ee003d0 Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. 
llvm-svn: 189698
 2013-08-30 21:19:48 +00:00
Elena Demikhovsky 003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Kevin Enderby 35fd79237f Update the X86 disassembler to use xacquire and xrelease when appropriate. 
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859

llvm-svn: 184490
 2013-06-20 22:32:18 +00:00
NAKAMURA Takumi f87f70a72d X86DisassemblerDecoder.c: Make this C89-compliant. 
llvm-svn: 177910
 2013-03-25 20:55:49 +00:00
NAKAMURA Takumi dde7fa838e Whitespace. 
llvm-svn: 177909
 2013-03-25 20:55:43 +00:00
Dave Zarzycki 07fabeecad x86 -- disassemble the REP/REPNE prefix when needed 
This fixes Apple bug: 13493622

llvm-svn: 177887
 2013-03-25 18:59:38 +00:00
Joerg Sonnenberger 2b86e48b3a Fix typo 
llvm-svn: 166945
 2012-10-29 17:56:15 +00:00
Craig Topper 963305b450 Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. 
llvm-svn: 163774
 2012-09-13 05:45:42 +00:00
Roman Divacky 6792380e7b Use const properly so that we dont remove const qualifier from region and MII 
by casting. Found with gcc48.

llvm-svn: 163247
 2012-09-05 21:17:34 +00:00
Richard Smith 228e6d4cf3 Fix integer undefined behavior due to signed left shift overflow in LLVM. 
Reviewed offline by chandlerc.

llvm-svn: 162623
 2012-08-24 23:29:28 +00:00
Craig Topper b8aec08819 Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. 
llvm-svn: 161101
 2012-08-01 07:39:18 +00:00
Craig Topper 7629d63bc4 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Benjamin Kramer adfc73d68f C files in llvm still have to be C89 compliant, remove C++-style comments. 
llvm-svn: 152495
 2012-03-10 15:10:06 +00:00
Kevin Enderby 014e1cde5f Fix the x86 disassembler to at least print the lock prefix if it is the first 
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414
 2012-03-09 17:52:49 +00:00
Craig Topper 6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target. 
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
 2012-02-23 18:18:17 +00:00
Ahmed Charles 636a3d618c Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
llvm-svn: 150918
 2012-02-19 11:37:01 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Benjamin Kramer 915e3d9568 Don't mix declarations and code. 
llvm-svn: 150305
 2012-02-11 16:01:02 +00:00
Benjamin Kramer 478e8de8ef Reuse the enum names from X86Desc in the X86Disassembler. 
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303
 2012-02-11 14:50:54 +00:00
Craig Topper a0cd970b81 More tweaks to get the size of the X86 disassembler tables down. 
llvm-svn: 150167
 2012-02-09 08:58:07 +00:00
Craig Topper 487e744f66 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
llvm-svn: 150161
 2012-02-09 07:45:30 +00:00
Duncan Sands ae22c60f90 Persuade GCC that there is nothing worth warning about here (there isn't). 
llvm-svn: 149834
 2012-02-05 14:20:11 +00:00
David Blaikie edbb58c577 Remove unnecessary default cases in switches that cover all enum values. 
llvm-svn: 147855
 2012-01-10 16:47:17 +00:00
Benjamin Kramer 9c48f26341 Silence warnings of a mysterious compiler that still defaults to C89. 
llvm-svn: 147553
 2012-01-04 22:06:45 +00:00
Benjamin Kramer 47aecca51a X86Disassembler: Fix undefined behavior found by GCC 4.6 
llvm-svn: 147404
 2012-01-01 17:55:36 +00:00
Craig Topper 2ba766ae84 Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper f01f1b5cb9 More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Craig Topper b58a9665bd Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey. 
llvm-svn: 141162
 2011-10-05 03:29:32 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00