b25fda95f6
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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llvm-svn: 152997
2012-03-17 18:46:09 +00:00
e1d619691b
some comment fix for X86 and ARM
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llvm-svn: 150902
2012-02-19 02:03:36 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
1b81fddd65
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
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llvm-svn: 150008
2012-02-07 22:50:41 +00:00
ebd90c58e6
Begin fleshing out more convenience predicates in llvm::Triple and
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convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.
This round of predicates is focused on OS-categorization predicates.
llvm-svn: 149815
2012-02-05 08:26:40 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
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Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
b0c0f72ae6
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE.
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llvm-svn: 147843
2012-01-10 06:54:16 +00:00
d97bbd7b60
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks.
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llvm-svn: 147842
2012-01-10 06:37:29 +00:00
eb8f9e9e5b
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
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llvm-svn: 147841
2012-01-10 06:30:56 +00:00
f287a4509e
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
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llvm-svn: 147770
2012-01-09 09:02:13 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
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llvm-svn: 146246
2011-12-09 06:32:46 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
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if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
1280eb1d06
Add XOP feature flag.
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llvm-svn: 145682
2011-12-02 15:14:37 +00:00
f563977795
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
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llvm-svn: 145053
2011-11-22 00:44:41 +00:00
228d9131aa
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
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llvm-svn: 143319
2011-10-30 19:57:21 +00:00
49045ddb4c
Remove NaClMode
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llvm-svn: 142338
2011-10-18 05:29:23 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141854
2011-10-13 07:09:14 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
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llvm-svn: 141651
2011-10-11 06:44:02 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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llvm-svn: 141505
2011-10-09 07:31:39 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
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instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
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llvm-svn: 138660
2011-08-26 21:21:21 +00:00
b66d255595
X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.
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llvm-svn: 135564
2011-07-20 04:02:20 +00:00
60fc0fca5c
Restore old behavior. Always auto-detect features unless cpu or features are specified.
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llvm-svn: 134757
2011-07-08 22:30:25 +00:00
13bcc6c1c7
Add Mode64Bit feature and sink it down to MC layer.
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llvm-svn: 134641
2011-07-07 21:06:52 +00:00
1a72add615
Compute feature bits at time of MCSubtargetInfo initialization.
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llvm-svn: 134606
2011-07-07 07:07:08 +00:00
c9c090d7a5
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
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llvm-svn: 134281
2011-07-01 22:36:09 +00:00
0d639a28aa
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
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llvm-svn: 134259
2011-07-01 21:01:15 +00:00
54b68e3432
- Added MCSubtargetInfo to capture subtarget features and scheduling
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itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
llvm-svn: 134257
2011-07-01 20:45:01 +00:00
fe6e405e8c
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
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be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
llvm-svn: 134127
2011-06-30 01:53:36 +00:00
3a0c5e52ff
Remove TargetOptions.h dependency from X86Subtarget.
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llvm-svn: 133726
2011-06-23 17:54:54 +00:00
2b9b0e3748
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
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predicates.
llvm-svn: 129816
2011-04-19 21:14:45 +00:00
100455a3c8
Target/X86: Eliminate uses of getDarwinVers().
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llvm-svn: 129813
2011-04-19 21:04:12 +00:00
44b530369d
Target/X86: Add getTargetTriple() accessor.
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llvm-svn: 129812
2011-04-19 21:01:47 +00:00
e8a93fe8f0
Stack alignment is 16 bytes on FreeBSD/i386 too.
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llvm-svn: 126226
2011-02-22 17:30:05 +00:00
bda7175a43
The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.
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llvm-svn: 126130
2011-02-21 17:37:17 +00:00
4c14a5cc2c
Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.
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No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.
llvm-svn: 125747
2011-02-17 12:24:17 +00:00
0544fe7287
Fix whitespace.
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llvm-svn: 125746
2011-02-17 12:23:50 +00:00
d22a4a1fd6
Patches to build EFI with Clang/LLVM. By Carl Norum.
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llvm-svn: 124639
2011-02-01 01:14:13 +00:00
8b08f5232b
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
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llvm-svn: 121439
2010-12-10 00:26:57 +00:00
2f489236ab
Add patterns for the x86 popcnt instruction.
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- Also adds a new POPCNT subtarget feature that is currently enabled if the target
supports SSE4.2 (nehalem) or SSE4A (barcelona).
llvm-svn: 120917
2010-12-04 20:32:23 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
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so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
ea639aa11f
X86Subtarget.h: Fix Cygwin's TD.
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llvm-svn: 114297
2010-09-18 19:50:42 +00:00
a5a645559c
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
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Patch by Cameron Esfahani!
llvm-svn: 112902
2010-09-02 23:03:46 +00:00
09dc24beac
Add x86 CLMUL (Carry-less multiplication) cpu feature
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llvm-svn: 109206
2010-07-23 01:17:51 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
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llvm-svn: 107625
2010-07-05 19:26:33 +00:00
dc53f1cb5c
FastISel doesn't yet handle callee-pop functions.
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To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
2010-05-27 18:43:40 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
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llvm-svn: 102493
2010-04-28 08:30:49 +00:00
9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
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llvm-svn: 101979
2010-04-21 01:47:12 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
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a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
738b0f9ec7
Nehalem unaligned memory access is fast.
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llvm-svn: 100089
2010-04-01 05:58:17 +00:00
bf724b9ee0
Turning off post-ra scheduling for x86. It isn't a consistent win.
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llvm-svn: 98810
2010-03-18 06:55:42 +00:00
a30d4ce194
add support for pentium class CPUs which do not have cmov,
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PR4841. Patch by Craig Smith!
llvm-svn: 98496
2010-03-14 18:31:44 +00:00
abd56bde0e
80-col violations/trailing whitespace.
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llvm-svn: 97427
2010-02-28 22:54:30 +00:00
c3c357006e
Setup correct data layout to match gcc's expectations on mingw32.
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llvm-svn: 95981
2010-02-12 15:28:56 +00:00
0067d6bbbe
Fix typo.
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llvm-svn: 93235
2010-01-12 08:30:46 +00:00
fd75e12954
Tweak commit 91745, which changed target data for both Mingw and Cygwin,
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to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size. Patch by Aaron Gray.
llvm-svn: 93234
2010-01-12 08:21:07 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
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ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
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llvm-svn: 91910
2009-12-22 17:47:23 +00:00
148d87b0b0
Bump alignment requirements for windows targets to achieve compartibility with vcpp.
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Based on patch by Michael Beck!
llvm-svn: 91745
2009-12-19 02:04:23 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
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be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
7a6611793f
Target-independent support for TargetFlags on BlockAddress operands,
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and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
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llvm-svn: 88682
2009-11-13 19:52:48 +00:00
0d412c2528
Fixed to address code review. No functional changes.
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llvm-svn: 86634
2009-11-10 00:48:55 +00:00
cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
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llvm-svn: 86628
2009-11-10 00:15:47 +00:00
8714348afd
indicate what the native integer types for the target are.
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Please verify.
llvm-svn: 86397
2009-11-07 19:07:32 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
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llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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llvm-svn: 84911
2009-10-22 23:19:17 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
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llvm-svn: 84431
2009-10-18 19:57:27 +00:00
936d87b39d
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
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llvm-svn: 84425
2009-10-18 18:31:31 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
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llvm-svn: 84273
2009-10-16 21:06:15 +00:00
e4a2117161
Remove X86Subtarget::IsLinux. It's no longer being used.
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llvm-svn: 84200
2009-10-15 20:23:21 +00:00
46dcaadb4a
rearrange X86ATTAsmPrinter::doFinalization, making a scan of
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the global variable list only happen for COFF targets.
llvm-svn: 82010
2009-09-16 05:20:33 +00:00
c3a0aba120
Make these functions static and local.
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llvm-svn: 80892
2009-09-03 05:47:34 +00:00
47455a79ae
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
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No functionality changes.
llvm-svn: 80880
2009-09-03 04:37:05 +00:00
cc8c581a5b
Add support for modeling whether or not the processor has support for
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conditional moves as a subtarget feature. This is the easy part of
PR4841.
llvm-svn: 80763
2009-09-02 05:53:04 +00:00
1e9097e36a
change the -x86-asm-syntax=intel/att flag to be in X86TAI
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instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
llvm-svn: 78746
2009-08-11 23:01:09 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
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Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
21c2940553
remove the now-dead TM argument to these methods.
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llvm-svn: 75276
2009-07-10 21:00:45 +00:00
ba4d73310a
make PIC vs DynamicNoPIC be explicit in PICStyles.
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llvm-svn: 75275
2009-07-10 20:58:47 +00:00
e2f524f176
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
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llvm-svn: 75273
2009-07-10 20:47:30 +00:00
20073edf67
simplify fast isel by using ClassifyGlobalReference. This
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elimiantes the last use of GVRequiresExtraLoad, so delete it.
llvm-svn: 75244
2009-07-10 07:48:51 +00:00
93f0f79178
eliminate GVRequiresRegister, replacing it with predicates we
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need for other purposes.
llvm-svn: 75243
2009-07-10 07:38:24 +00:00
dc842c06c2
move some classification logic around. Now GVRequiresExtraLoad
...
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
llvm-svn: 75237
2009-07-10 07:20:05 +00:00
b9af63a4d2
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
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llvm-svn: 75232
2009-07-10 05:52:02 +00:00
ace6ec26d9
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
...
more complex and slow than just directly testing what we care about.
llvm-svn: 75231
2009-07-10 05:48:03 +00:00
7277a807f0
There is only one case where GVRequiresExtraLoad returns true for calls:
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split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
llvm-svn: 75230
2009-07-10 05:45:15 +00:00
1cc7ae7c3b
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
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llvm-svn: 75229
2009-07-10 05:37:11 +00:00
1c5bf9d26d
When in -static mode, force the PIC style to none. Doing this requires fixing
...
code which conflated RIPRel PIC with x86-64. Fix these to just check for X86-64
directly.
llvm-svn: 75092
2009-07-09 03:15:51 +00:00
a4b8998fbb
Fix a subtarget feature bug.
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llvm-svn: 74428
2009-06-29 16:51:01 +00:00
8f6f72cc99
Add feature flags for AVX and FMA and fix some SSE4A feature flag
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initialization problems.
llvm-svn: 74350
2009-06-26 22:46:54 +00:00
cfad3f3807
cosmetic changes.
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llvm-svn: 73836
2009-06-21 01:27:55 +00:00
96180b5387
Update CPU capabilities for AMD machines
...
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
08bf4c0f5a
Propagate CPU string out of SubtargetFeatures
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llvm-svn: 72335
2009-05-23 19:50:50 +00:00
960983371c
Try again. Allow call to immediate address for ELF or when in static relocation mode.
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llvm-svn: 72160
2009-05-20 04:53:57 +00:00
906152a20f
Tidy up #includes, deleting a bunch of unnecessary #includes.
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llvm-svn: 61715
2009-01-05 17:59:02 +00:00
Craig Topper