Commit Graph

22513 Commits

Author SHA1 Message Date
David Woodhouse 71d15edaf3 [x86] Support i386-*-*-code16 triple for emitting 16-bit code
llvm-svn: 199648
2014-01-20 12:02:25 +00:00
Chandler Carruth 4d35631a6c [PM] Wire up the Verifier for the new pass manager and connect it to the
various opt verifier commandline options.

Mostly mechanical wiring of the verifier to the new pass manager.
Exercises one of the more unusual aspects of it -- a pass can be either
a module or function pass interchangably. If this is ever problematic,
we can make things more constrained, but for things like the verifier
where there is an "obvious" applicability at both levels, it seems
convenient.

This is the next-to-last piece of basic functionality left to make the
opt commandline driving of the new pass manager minimally functional for
testing and further development. There is still a lot to be done there
(notably the factoring into .def files to kill the current boilerplate
code) but it is relatively uninteresting. The only interesting bit left
for minimal functionality is supporting the registration of analyses.
I'm planning on doing that on top of the .def file switch mostly because
the boilerplate for the analyses would be significantly worse.

llvm-svn: 199646
2014-01-20 11:34:08 +00:00
Kai Nacke e51c813859 ARM: add tlsldo relocation
Add support for the symbol(tlsldo) relocation. This is required in order to 
solve PR18554.

Reviewed by R. Golin, A. Korobeynikov.

llvm-svn: 199644
2014-01-20 11:00:40 +00:00
Artyom Skrobov 10e76a4eda [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is non-optional: it should have the default value of AllowDIVIfExists
llvm-svn: 199638
2014-01-20 10:18:42 +00:00
Chandler Carruth f835fc6f4f Revert r199628: "[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT."
This test fails the newly added regression tests.

llvm-svn: 199631
2014-01-20 08:18:01 +00:00
Owen Anderson 1664dc8973 Fix all the remaining lost-fast-math-flags bugs I've been able to find. The most important of these are cases in the generic logic for combining BinaryOperators.
This logic hadn't been updated to handle FastMathFlags, and it took me a while to detect it because it doesn't show up in a simple search for CreateFAdd.

llvm-svn: 199629
2014-01-20 07:44:53 +00:00
Kevin Qin ff42e06ef4 [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.
llvm-svn: 199628
2014-01-20 07:32:26 +00:00
Kevin Qin ef66ff78ca [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser.
For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be
printed as #0.0 instead of #0. To support the history codes using #0,
we consider to let asm parser accept both #0.0 and #0.

llvm-svn: 199621
2014-01-20 02:14:05 +00:00
Benjamin Kramer b80e1699b3 InstCombine: Modernize a bunch of cast combines.
Also make them vector-aware.

llvm-svn: 199608
2014-01-19 20:05:13 +00:00
Benjamin Kramer 7a74bd4703 InstCombine: Replace a hand-rolled version of isKnownToBeAPowerOfTwo with the real thing.
llvm-svn: 199604
2014-01-19 16:48:41 +00:00
Benjamin Kramer 72196f3ae5 InstCombine: Teach most integer add/sub/mul/div combines how to deal with vectors.
llvm-svn: 199602
2014-01-19 15:24:22 +00:00
Benjamin Kramer 76b15d04ff InstCombine: Refactor fmul/fdiv combines to handle vectors.
llvm-svn: 199598
2014-01-19 13:36:27 +00:00
Chandler Carruth 1bf38c6a71 Fix a really nasty SROA bug with how we handled out-of-bounds memcpy
intrinsics.

Reported on the list by Evan with a couple of attempts to fix, but it
took a while to dig down to the root cause. There are two overlapping
bugs here, both centering around the circumstance of discovering
a memcpy operand which is known to be completely outside the bounds of
the alloca.

First, we need to kill the *other* side of the memcpy if it was added to
this alloca. Otherwise we'll factor it into our slicing and try to
rewrite it even though we know for a fact that it is dead. This is made
more tricky because we can visit the sides in either order. So we have
to both kill the other side and skip instructions marked as dead. The
latter really should be goodness in every case, but here is a matter of
correctness.

Second, we need to actually remove the *uses* of the alloca by the
memcpy when queuing it for later deletion. Otherwise it may still be
using the alloca when we go to promote it (if the rewrite re-uses the
existing alloca instruction). Do this by factoring out the
use-clobbering used when for nixing a Phi argument and re-using it
across the operands of a to-be-deleted instruction.

llvm-svn: 199590
2014-01-19 12:16:54 +00:00
Saleem Abdulrasool 9390005577 ARM ELF: ensure that the tag types are corrected
Ensure that the tag types are reflected on a replacement.  This is particularly
important for the compatibility tag which has multiple representations where the
last definition wins.

llvm-svn: 199577
2014-01-19 08:25:41 +00:00
Saleem Abdulrasool 196c3212ba ARM: update build attributes for ABI r2.09
Update names for the names as per the current ABI errata.  Mark deprecated tags
as such.

llvm-svn: 199576
2014-01-19 08:25:35 +00:00
Arnold Schwaighofer cc742dd9e4 LoopVectorizer: A reduction that has multiple uses of the reduction value is not
a reduction.

Really. Under certain circumstances (the use list of an instruction has to be
set up right - hence the extra pass in the test case) we would not recognize
when a value in a potential reduction cycle was used multiple times by the
reduction cycle.

Fixes PR18526.
radar://15851149

llvm-svn: 199570
2014-01-19 03:18:31 +00:00
Chandler Carruth 043949d446 [PM] Make the verifier work independently of any pass manager.
This makes the 'verifyFunction' and 'verifyModule' functions totally
independent operations on the LLVM IR. It also cleans up their API a bit
by lifting the abort behavior into their clients and just using an
optional raw_ostream parameter to control printing.

The implementation of the verifier is now just an InstVisitor with no
multiple inheritance. It also is significantly more const-correct, and
hides the const violations internally. The two layers that force us to
break const correctness are building a DomTree and dispatching through
the InstVisitor.

A new VerifierPass is used to implement the legacy pass manager
interface in terms of the other pieces.

The error messages produced may be slightly different now, and we may
have slightly different short circuiting behavior with different usage
models of the verifier, but generally everything works equivalently and
this unblocks wiring the verifier up to the new pass manager.

llvm-svn: 199569
2014-01-19 02:22:18 +00:00
Nick Lewycky a6a17d77d2 Don't refuse to transform constexpr(call(arg, ...)) to call(constexpr(arg), ...)) just because the function has multiple return values even if their return types are the same. Patch by Eduard Burtescu!
llvm-svn: 199564
2014-01-18 22:47:12 +00:00
Benjamin Kramer dd39a98b1c ARM: Let the assembler reject v5 instructions in v4 mode.
PR18524.

llvm-svn: 199559
2014-01-18 19:03:19 +00:00
NAKAMURA Takumi 3189afc4ca [CMake] Add llvm-tblgen to dependencies of check-llvm.
llvm-tblgen is not built when external LLVM_TABLEGEN is specified.
Even then, llvm-tblgen should be built for testing tblgen itself.

llvm-svn: 199558
2014-01-18 19:01:08 +00:00
Benjamin Kramer fea9ac99b0 InstCombine: Make the (fmul X, -1.0) -> (fsub -0.0, X) transform handle vectors too.
PR18532.

llvm-svn: 199553
2014-01-18 16:43:14 +00:00
Adrian Prantl ef129fbb41 Debug info (LTO): Move the creation of accessibility flags to
getOrCreateSubprogramDIE to avoid attributes being added twice when DIEs
are merged.

rdar://problem/15842330.

llvm-svn: 199536
2014-01-18 02:12:00 +00:00
Owen Anderson 48b842ef7c Fix more instances of dropped fast math flags when optimizing FADD instructions. All found by inspection (aka grep).
llvm-svn: 199528
2014-01-18 00:48:14 +00:00
Reid Kleckner 436c42ec3d Add an inalloca flag to allocas
Summary:
The only current use of this flag is to mark the alloca as dynamic, even
if its in the entry block.  The stack adjustment for the alloca can
never be folded into the prologue because the call may clear it and it
has to be allocated at the top of the stack.

Reviewers: majnemer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2571

llvm-svn: 199525
2014-01-17 23:58:17 +00:00
Rui Ueyama e5df6095b1 llvm-objdump/COFF: Print ordinal base number.
llvm-svn: 199518
2014-01-17 22:02:24 +00:00
Juergen Ributzka e625013071 Add two new calling conventions for runtime calls
This patch adds two new target-independent calling conventions for runtime
calls - PreserveMost and PreserveAll.
The target-specific implementation for X86-64 is defined as following:
  - Arguments are passed as for the default C calling convention
  - The same applies for the return value(s)
  - PreserveMost preserves all GPRs - except R11
  - PreserveAll preserves all GPRs and all XMMs/YMMs - except R11

Reviewed by Lang and Philip

llvm-svn: 199508
2014-01-17 19:47:03 +00:00
Daniel Sanders b825a634d6 [mips][msa] Correct pattern for LSA
Summary:
$rs and $rt were the wrong way round in the .td and the testcase wasn't
strict enough to detect the mistake.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2554

llvm-svn: 199498
2014-01-17 15:40:05 +00:00
Renato Golin afc43a1cbe Add MLA alias for ARMv4 support.
Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

llvm-svn: 199491
2014-01-17 13:53:08 +00:00
Kostya Serebryany 714c67c31e [asan] extend asan-coverage (still experimental).
- add a mode for collecting per-block coverage (-asan-coverage=2).
   So far the implementation is naive (all blocks are instrumented),
   the performance overhead on top of asan could be as high as 30%.
 - Make sure the one-time calls to __sanitizer_cov are moved to function buttom,
   which in turn required to copy the original debug info into the call insn.

Here is the performance data on SPEC 2006
(train data, comparing asan with asan-coverage={0,1,2}):

                             asan+cov0     asan+cov1      diff 0-1    asan+cov2       diff 0-2      diff 1-2
       400.perlbench,        65.60,        65.80,         1.00,        76.20,         1.16,         1.16
           401.bzip2,        65.10,        65.50,         1.01,        75.90,         1.17,         1.16
             403.gcc,         1.64,         1.69,         1.03,         2.04,         1.24,         1.21
             429.mcf,        21.90,        22.60,         1.03,        23.20,         1.06,         1.03
           445.gobmk,       166.00,       169.00,         1.02,       205.00,         1.23,         1.21
           456.hmmer,        88.30,        87.90,         1.00,        91.00,         1.03,         1.04
           458.sjeng,       210.00,       222.00,         1.06,       258.00,         1.23,         1.16
      462.libquantum,         1.73,         1.75,         1.01,         2.11,         1.22,         1.21
         464.h264ref,       147.00,       152.00,         1.03,       160.00,         1.09,         1.05
         471.omnetpp,       115.00,       116.00,         1.01,       140.00,         1.22,         1.21
           473.astar,       133.00,       131.00,         0.98,       142.00,         1.07,         1.08
       483.xalancbmk,       118.00,       120.00,         1.02,       154.00,         1.31,         1.28
            433.milc,        19.80,        20.00,         1.01,        20.10,         1.02,         1.01
            444.namd,        16.20,        16.20,         1.00,        17.60,         1.09,         1.09
          447.dealII,        41.80,        42.20,         1.01,        43.50,         1.04,         1.03
          450.soplex,         7.51,         7.82,         1.04,         8.25,         1.10,         1.05
          453.povray,        14.00,        14.40,         1.03,        15.80,         1.13,         1.10
             470.lbm,        33.30,        34.10,         1.02,        34.10,         1.02,         1.00
         482.sphinx3,        12.40,        12.30,         0.99,        13.00,         1.05,         1.06

llvm-svn: 199488
2014-01-17 11:00:30 +00:00
Kevin Qin e0faea11b1 [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.
llvm-svn: 199485
2014-01-17 09:54:30 +00:00
Craig Topper 2d4b3c9770 Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.
llvm-svn: 199477
2014-01-17 07:44:10 +00:00
Craig Topper 9ac290ad5b Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.
llvm-svn: 199476
2014-01-17 07:37:39 +00:00
Craig Topper a49c2960c6 Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q'
llvm-svn: 199474
2014-01-17 07:25:39 +00:00
Hao Liu 17457a2ee2 [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
Also add copy support for FPR16.
Also add a missing test case file belongs to commit r197361.

llvm-svn: 199463
2014-01-17 06:23:30 +00:00
Kevin Qin 212d9b4a56 [AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
llvm-svn: 199462
2014-01-17 05:52:35 +00:00
Hao Liu 18d92262c5 [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.

llvm-svn: 199461
2014-01-17 05:44:46 +00:00
Reid Kleckner 60d3a835ff Change inalloca rules to make it only apply to the last parameter
This makes things a lot easier, because we can now talk about the
"argument allocation", which allocates all the memory for the call in
one shot.

The only functional change is to the verifier for a feature that hasn't
shipped yet.

llvm-svn: 199434
2014-01-16 22:59:24 +00:00
Owen Anderson e7321660c1 Fix two cases where we could lose fast math flags when optimizing FADD expressions.
llvm-svn: 199427
2014-01-16 21:26:02 +00:00
Owen Anderson 4557a156e3 Fix an instance where we would drop fast math flags when performing an fdiv to reciprocal multiply transformation.
llvm-svn: 199425
2014-01-16 21:07:52 +00:00
Owen Anderson e8537fc7e0 Fix a bug in InstCombine where we failed to preserve fast math flags when optimizing an FMUL expression.
llvm-svn: 199424
2014-01-16 20:59:41 +00:00
Rui Ueyama da49d0d44c llvm-objdump/COFF: Print DLL name in the export table header.
llvm-svn: 199422
2014-01-16 20:50:34 +00:00
Owen Anderson f74cfe031f Teach InstCombine that (fmul X, -1.0) can be simplified to (fneg X), which LLVM expresses as (fsub -0.0, X).
llvm-svn: 199420
2014-01-16 20:36:42 +00:00
Ed Maste ef6fed7c84 llvm-symbolizer: make mangled name heuristic apply to all symbols
PR: http://llvm.org/pr18431
Review: http://llvm-reviews.chandlerc.com/D2552
llvm-svn: 199404
2014-01-16 17:25:12 +00:00
Amara Emerson dba59eb3f4 Move the xscale build attribute test to the proper place and remove the old one.
The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s

llvm-svn: 199393
2014-01-16 15:11:54 +00:00
Jiangning Liu 4df2363a23 For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.
llvm-svn: 199369
2014-01-16 09:16:13 +00:00
Elena Demikhovsky d1487261a0 AVX-512: fixed a compare pattern
llvm-svn: 199366
2014-01-16 08:45:54 +00:00
Craig Topper 35da3d190a Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
Bill Wendling 2f98bac1f4 Fix typo: : not ;
llvm-svn: 199359
2014-01-16 07:08:22 +00:00
Rui Ueyama ad882ba896 llmv-objdump/COFF: Print export table contents.
This patch adds the capability to dump export table contents. An example
output is this:

  Export Table:
   Ordinal      RVA  Name
         5   0x2008  exportfn1
         6   0x2010  exportfn2

By adding this feature to llvm-objdump, we will be able to use it to check
export table contents in LLD's tests. Currently we are doing binary
comparison in the tests, which is fragile and not readable to humans.

llvm-svn: 199358
2014-01-16 07:05:49 +00:00
Rafael Espindola 306e2b019f Convert test to FileCheck.
llvm-svn: 199355
2014-01-16 06:31:20 +00:00
Arnold Schwaighofer e3ac099726 BasicAA: We need to check both access sizes when comparing a gep and an
underlying object of unknown size.

Fixes PR18460.

llvm-svn: 199351
2014-01-16 04:53:18 +00:00
Manman Ren 2ebfb42fe9 Report a warning when dropping outdated debug info metadata.
Use DiagnosticInfo to emit the warning.

llvm-svn: 199346
2014-01-16 01:51:12 +00:00
Reed Kotler 43788a20c6 Adjust offsets for max load instruction offsets. This is more pessimistic
than it needs to be by 1 bit but I need to finish some other things so 
that all the boundary cases will work in that situation. constpool.c
in test-suite will fail to assemble under our new internal test-suite sync
without this change.

llvm-svn: 199343
2014-01-16 00:47:46 +00:00
David Peixotto c0f92a2dc9 Fix parsing of .symver directive on ARM
ARM assembly syntax uses @ for a comment, execpt for the second
parameter of the .symver directive which requires @ as part of the
symbol name. This commit fixes the parsing of this directive by
adding a special case for ARM for this one argumnet.

To make the change we had to move the AllowAtInIdentifier variable
to the MCAsmLexer interface (from AsmLexer) and expose a setter for
the value.  The ELFAsmParser then toggles this value when parsing
the second argument to the .symver directive for a target that
uses @ as a comment symbol

llvm-svn: 199339
2014-01-15 22:40:02 +00:00
Andrea Di Biagio 12de5f3bc1 Update test/CodeGen/X86/vbinop-simplify-bug.ll.
Redirect the output of llc to /dev/null.

llvm-svn: 199329
2014-01-15 20:16:14 +00:00
Andrea Di Biagio d7c03ec348 [DAGCombiner] Fix a wrong check in method SimplifyVBinOp.
This fixes a regression intruced by r199135.

Revision 199135 tried to simplify part of the logic in method
DAGCombiner::SimplifyVBinOp introducing calls to method BuildVectorSDNode::isConstant().

However, that revision wrongly changed the check performed by method
SimplifyVBinOp to identify dag nodes that can be folded.
Before revision 199135, that method only tried to simplify vector binary operations
if both operands were build_vector of Constant/ConstantFP/Undef only.

After revision 199135, method SimplifyVBinop tried to
simplify also vector binary operations with only one constant operand.

This fixes the problem restoring the old behavior of SimplifyVBinOp.

llvm-svn: 199328
2014-01-15 19:51:32 +00:00
Kevin Enderby 2e13b1c7f1 Update the X86 assembler for .intel_syntax to accept
the | and & bitwise operators.

rdar://15570412

llvm-svn: 199323
2014-01-15 19:05:24 +00:00
Rafael Espindola 587940502b Make sure we create a new archive by deleting any stale ones first.
llvm-svn: 199319
2014-01-15 16:56:57 +00:00
Zoran Jovanovic 7d63392da9 LL and SC decoder method fix.
llvm-svn: 199316
2014-01-15 13:17:33 +00:00
Zoran Jovanovic d4cb61cf0e Added support for LWU microMIPS instruction.
llvm-svn: 199315
2014-01-15 13:01:18 +00:00
David Majnemer dee105772c WinCOFF: Transform IR expressions featuring __ImageBase into image relative relocations
MSVC on x64 requires that we create image relative symbol
references to refer to RTTI data. Seeing as how there is no way to
explicitly make reference to a given relocation type in LLVM IR, pattern
match expressions of the form &foo - &__ImageBase.

Differential Revision: http://llvm-reviews.chandlerc.com/D2523

llvm-svn: 199312
2014-01-15 09:16:42 +00:00
Renato Golin da3b5987ca Revert 199262 - MCJIT remote still failing on ARM
Disabling remote MCJIT tests on ARM again, as they're still failing when
self-hosting on ARM, despite all my tests. At least now we have more info
on what message it's breaking and what is going on. Investigating.

llvm-svn: 199310
2014-01-15 09:09:46 +00:00
Renato Golin f7eddfeab5 Re-disable MCJIT remote tests on ARM
llvm-svn: 199309
2014-01-15 09:09:39 +00:00
Andrew Trick ee5aa7f71a Fix PR18449: SCEV needs more precise max BECount for multi-exit loop.
llvm-svn: 199299
2014-01-15 06:42:11 +00:00
Jiangning Liu 0a791c348b For AArch64, lowering sext_inreg and generate optimized code by using SXTL.
llvm-svn: 199296
2014-01-15 05:08:01 +00:00
Hans Wennborg 4744ac1733 Switch-to-lookup tables: set threshold to 3 cases
There has been an old FIXME to find the right cut-off for when it's worth
analyzing and potentially transforming a switch to a lookup table.

The switches always have two or more cases. I could not measure any speed-up
by transforming a switch with two cases. A switch with three cases gets a nice
speed-up, and I couldn't measure any compile-time regression, so I think this
is the right threshold.

In a Clang self-host, this causes 480 new switches to be transformed,
and reduces the final binary size with 8 KB.

llvm-svn: 199294
2014-01-15 05:00:27 +00:00
Arnold Schwaighofer dc4c9460a2 LoopVectorize: Only strip casts from integer types when replacing symbolic
strides

Fixes PR18480.

llvm-svn: 199291
2014-01-15 03:35:46 +00:00
Rafael Espindola 26e917cde0 Only mark functions as micromips.
The GNU as behavior is a bit different and very strange. It will mark any
label that contains an instruction. We can implement that, but using the
type looks more natural since gas will not mark a function if a .word is
used to output the instructions!

llvm-svn: 199287
2014-01-15 03:07:12 +00:00
Weiming Zhao fe26fd27b4 PR 18466: Fix ARM Pseudo Expansion
When expanding neon pseudo stores, it may miss the implicit uses of sub
regs, which may cause post RA scheduler reorder instructions that
breakes anti dependency.

For example:
  VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
  will be expanded to
    VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;

An instruction that defines %D20 may be scheduled before the store by
mistake.

This patches adds implicit uses for such case. For the example above, it
emits:
  VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg, %Q9_Q10<imp-use>

llvm-svn: 199282
2014-01-15 01:32:12 +00:00
Eric Christopher 1ad8457570 Make sure we emit a relocation to the debug_ranges section in the
presence of CU ranges.

llvm-svn: 199276
2014-01-15 00:04:29 +00:00
Eric Christopher fb4a99cd0a Add testcase for r199263 forgotten in commit.
llvm-svn: 199267
2014-01-14 22:57:52 +00:00
Tim Northover 463a5f24d1 ARM: correctly determine final tBX_LR in Thumb1 functions
The changes caused by folding an sp-adjustment into a "pop" previously
disrupted the forward search for the final real instruction in a
terminating block. This switches to a backward search (skipping debug
instrs).

This fixes PR18399.

Patch by Zhaoshi.

llvm-svn: 199266
2014-01-14 22:53:28 +00:00
Tim Northover 6e219cd588 AArch64: don't try to handle [SU]MUL_LOHI nodes
We should set them to expand for now since there are no patterns
dealing with them. Actually, there are no instructions either so I
doubt they'll ever be acceptable.

llvm-svn: 199265
2014-01-14 22:53:22 +00:00
Renato Golin 4086bf7156 Re-enable remote MCJIT tests on ARMv7
llvm-svn: 199262
2014-01-14 22:43:49 +00:00
Matt Arsenault 2d353d1a10 Do pointer cast simplifications on addrspacecast
llvm-svn: 199254
2014-01-14 20:00:45 +00:00
Rafael Espindola 08ff298d51 Revert "[AArch64] Added vselect patterns with float and double types"
This reverts commit r199242.

It is causing CodeGen/AArch64/neon-bsl.ll to fail.

llvm-svn: 199248
2014-01-14 19:24:08 +00:00
Matt Arsenault e55a2c2e6b Make nocapture analysis work with addrspacecast
llvm-svn: 199246
2014-01-14 19:11:52 +00:00
Rafael Espindola 6633d57ae4 Fix a low hanging use of hasRawTextSupport.
This also fixes the placement of the function label comment. It was being
placed next to the mips16 directive instead of next to the label.

llvm-svn: 199245
2014-01-14 18:57:12 +00:00
Ana Pazos 787f540daa [AArch64] Added vselect patterns with float and double types
llvm-svn: 199242
2014-01-14 18:45:48 +00:00
Zoran Jovanovic 9d176af731 Test case micromips-load-effective-address.s renamed to micromips-load-effective-address.ll and moved to test/CodeGen/Mips.
llvm-svn: 199221
2014-01-14 16:26:47 +00:00
Nico Rieck c60647f0db Handle dllexport for global aliases
llvm-svn: 199219
2014-01-14 15:23:25 +00:00
Nico Rieck 7157bb765e Decouple dllexport/dllimport from linkage
Representing dllexport/dllimport as distinct linkage types prevents using
these attributes on templates and inline functions.

Instead of introducing further mixed linkage types to include linkonce and
weak ODR, the old import/export linkage types are replaced with a new
separate visibility-like specifier:

  define available_externally dllimport void @f() {}
  @Var = dllexport global i32 1, align 4

Linkage for dllexported globals and functions is now equal to their linkage
without dllexport. Imported globals and functions must be either
declarations with external linkage, or definitions with
AvailableExternallyLinkage.

llvm-svn: 199218
2014-01-14 15:22:47 +00:00
Elena Demikhovsky 767fc967b4 AVX-512: optimized scalar compare patterns
removed AVX512SI format, since it is similar to AVX512BI.

llvm-svn: 199217
2014-01-14 15:10:08 +00:00
Andrea Di Biagio 5448a3c771 [X86] Fix assertion failure caused by a wrong folding of vector shifts by immediate count.
This fixes a regression intruced by r198113.

Revision r198113 introduced an algorithm that tries to fold a vector shift
by immediate count into a build_vector if the input vector is a known vector
of constants.

However the algorithm only worked under the assumption that the input vector
type and the shift type are exactly the same.

This patch disables the folding of vector shift by immediate count if the
input vector type and the shift value type are not the same.

llvm-svn: 199213
2014-01-14 13:17:12 +00:00
Tim Northover 56cc5c92db ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts.
llvm-svn: 199212
2014-01-14 13:05:47 +00:00
Nico Rieck 9d2e0df049 Revert "Decouple dllexport/dllimport from linkage"
Revert this for now until I fix an issue in Clang with it.

This reverts commit r199204.

llvm-svn: 199207
2014-01-14 12:38:32 +00:00
Nico Rieck 1794b62f54 Revert "Handle dllexport for global aliases"
This reverts commit r199205.

llvm-svn: 199206
2014-01-14 12:36:54 +00:00
Nico Rieck 4192acdbc3 Handle dllexport for global aliases
llvm-svn: 199205
2014-01-14 11:55:40 +00:00
Nico Rieck e43aaf7967 Decouple dllexport/dllimport from linkage
Representing dllexport/dllimport as distinct linkage types prevents using
these attributes on templates and inline functions.

Instead of introducing further mixed linkage types to include linkonce and
weak ODR, the old import/export linkage types are replaced with a new
separate visibility-like specifier:

  define available_externally dllimport void @f() {}
  @Var = dllexport global i32 1, align 4

Linkage for dllexported globals and functions is now equal to their linkage
without dllexport. Imported globals and functions must be either
declarations with external linkage, or definitions with
AvailableExternallyLinkage.

llvm-svn: 199204
2014-01-14 11:55:03 +00:00
Jakob Stoklund Olesen b6b35a4955 Always let value types influence register classes.
When creating a virtual register for a def, the value type should be
used to pick the register class. If we only use the register class
constraint on the instruction, we might pick a too large register class.

Some registers can store values of different sizes. For example, the x86
xmm registers can hold f32, f64, and 128-bit vectors. The three
different value sizes are represented by register classes with identical
register sets: FR32, FR64, and VR128. These register classes have
different spill slot sizes, so it is important to use the right one.

The register class constraint on an instruction doesn't necessarily care
about the size of the value its defining. The value type determines
that.

This fixes a problem where InstrEmitter was picking 32-bit register
classes for 64-bit values on SPARC.

llvm-svn: 199187
2014-01-14 06:18:38 +00:00
Rafael Espindola 6d5f7ce348 Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips".
This matches what gnu as does and implementing this is easier than arguing
about it.

llvm-svn: 199181
2014-01-14 04:25:13 +00:00
Mark Seaborn 8271118a65 Fix llc to not reuse spill slots in functions that invoke setjmp()
We need to ensure that StackSlotColoring.cpp does not reuse stack
spill slots in functions that call "returns_twice" functions such as
setjmp(), otherwise this can lead to miscompiled code, because a stack
slot would be clobbered when it's still live.

This was already handled correctly for functions that call setjmp()
(though this wasn't covered by a test), but not for functions that
invoke setjmp().

We fix this by changing callsFunctionThatReturnsTwice() to check for
invoke instructions.

This fixes PR18244.

llvm-svn: 199180
2014-01-14 04:20:01 +00:00
Cameron McInally da3bba445b Clean up RUN command for Assembler/getInt.ll.
llvm-svn: 199158
2014-01-13 22:37:35 +00:00
Cameron McInally f0379fa41a Fix uninitialized warning in llvm/lib/IR/DataLayout.cpp.
llvm-svn: 199147
2014-01-13 22:04:55 +00:00
Juergen Ributzka 7384405f23 [DAG] Teach DAG to also reassociate vector operations
This commit teaches DAG to reassociate vector ops, which in turn enables
constant folding of vector op chains that appear later on during custom lowering
and DAG combine.

Reviewed by Andrea Di Biagio

llvm-svn: 199135
2014-01-13 20:51:35 +00:00
Weiming Zhao f66be56bf7 Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks
The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().

llvm-svn: 199127
2014-01-13 18:47:54 +00:00
Andrea Di Biagio 9bc0415c1f [AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.

llvm-svn: 199119
2014-01-13 16:51:00 +00:00
Richard Sandiford 36b376914d [SystemZ] Flesh out stackrestore test (frame-11.ll)
...so that it does something vaguely sensible.

llvm-svn: 199117
2014-01-13 15:44:44 +00:00
Richard Sandiford 9b9e057ced [SystemZ] Add "volatile" to a dead store in variable-loc.ll
llvm-svn: 199116
2014-01-13 15:42:16 +00:00
Richard Sandiford 64c0c4c015 [SystemZ] Improve risbg-01.ll test
The old mask in f24 wasn't well chosen because the lshr would always be zero.
CodeGen didn't detect this but InstCombine would.  The new mask ensures
that both shifts are needed.

f26 is specifically testing for a wrap-around mask.  The AND can be applied
to just the shift left, either before or after the shift.  Again, CodeGen
kept it in the original form but InstCombine would mask after the shift
instead.  The exact choice of NILF isn't important for the test so I just
dropped it and kept the rotate.

llvm-svn: 199115
2014-01-13 15:40:25 +00:00
Richard Sandiford 32379b8141 [SystemZ] Optimize (sext (ashr (shl ...), ...))
...into (ashr (shl (anyext X), ...), ...), which requires one fewer
instruction.  The (anyext X) can sometimes be simplified too.

I didn't do this in DAGCombiner because widening shifts isn't a win
on all targets.

llvm-svn: 199114
2014-01-13 15:17:53 +00:00
Tim Northover 7d074a5ad6 ARM: add test for r199108. Oops.
rdar://problem/15800156

llvm-svn: 199109
2014-01-13 14:20:25 +00:00
David Woodhouse 4e033b0e92 [x86] Fix retq/retl handling in 64-bit mode
This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

llvm-svn: 199106
2014-01-13 14:05:59 +00:00
Elena Demikhovsky b19c9dc1a1 AVX-512: Embedded Rounding Control - encoding and printing
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

llvm-svn: 199102
2014-01-13 12:55:03 +00:00
Chandler Carruth b7bdfd65ac [PM] Wire up support for writing bitcode with new PM.
This moves the old pass creation functionality to its own header and
updates the callers of that routine. Then it adds a new PM supporting
bitcode writer to the header file, and wires that up in the opt tool.
A test is added that round-trips code into bitcode and back out using
the new pass manager.

llvm-svn: 199078
2014-01-13 07:38:24 +00:00
NAKAMURA Takumi eccd28d519 llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and mkdir(1) at the top.
llvm-svn: 199077
2014-01-13 05:55:10 +00:00
Chandler Carruth b353c3f7f2 [PM] Wire up support for printing assembly output from the opt command.
This lets us round-trip IR in the expected manner with the opt tool.

llvm-svn: 199075
2014-01-13 05:16:45 +00:00
Kevin Qin cfef55d6d4 [AArch64 NEON] Add missing patterns for bitcast from or to v1f64
llvm-svn: 199070
2014-01-13 01:58:38 +00:00
Kevin Qin 21e8f1c4eb [AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector
This patch covered 2 more scenarios:

1.  Two operands of shuffle_vector are the same, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

2. One of operands is undef, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

After this patch, perm instructions will have chance to be emitted instead of lots of INS.

llvm-svn: 199069
2014-01-13 01:56:29 +00:00
Saleem Abdulrasool a6505ca4c2 correct target directive handling error handling
The target specific parser should return `false' if the target AsmParser handles
the directive, and `true' if the generic parser should handle the directive.
Many of the target specific directive handlers would `return Error' which does
not follow these semantics.  This change simply changes the target specific
routines to conform to the semantis of the ParseDirective correctly.

Conformance to the semantics improves diagnostics emitted for the invalid
directives.  X86 is taken as a sample to ensure that multiple diagnostics are
not presented for a single error.

llvm-svn: 199068
2014-01-13 01:15:39 +00:00
Jakob Stoklund Olesen 1995b9fead Handle bundled terminators in isBlockOnlyReachableByFallthrough.
Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.

Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.

llvm-svn: 199061
2014-01-12 19:24:08 +00:00
Nico Rieck f15341c9de Make test independent of scheduling
llvm-svn: 199055
2014-01-12 15:57:38 +00:00
NAKAMURA Takumi d7032ac21e llvm/test/CodeGen/X86/shl_undef.ll: Tweak to satisfy r199050.
Use intel syntax, or "shl" might hit "pushl".

llvm-svn: 199051
2014-01-12 14:41:41 +00:00
Nico Rieck b5262d6d8f Fix non-deterministic SDNodeOrder-dependent codegen
Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code
generation.

llvm-svn: 199050
2014-01-12 14:09:17 +00:00
Chandler Carruth 52eef8876e [PM] Add module and function printing passes for the new pass manager.
This implements the legacy passes in terms of the new ones. It adds
basic testing using explicit runs of the passes. Next up will be wiring
the basic output mechanism of opt up when the new pass manager is
engaged unless bitcode writing is requested.

llvm-svn: 199049
2014-01-12 12:15:39 +00:00
Chandler Carruth 6546cb6313 [PM] Fix a bunch of bugs I spotted by inspection when working on this
code. Copious tests added to cover these cases.

llvm-svn: 199039
2014-01-12 10:02:02 +00:00
Chandler Carruth d833098d17 [PM] Add support for parsing function passes and function pass manager
nests to the opt commandline support. This also showcases the
implicit-initial-manager support which will be most useful for testing.
There are several bugs that I spotted by inspection here that I'll fix
with test cases in subsequent commits.

llvm-svn: 199038
2014-01-12 09:34:22 +00:00
Saleem Abdulrasool bdae4b8743 ARM IAS: fix diagnostics of improper qualification
An improper qualifier would result in a superfluous error due to the parser not
consuming the remainder of the statement.  Simply consume the remainder of the
statement to avoid the error.

llvm-svn: 199035
2014-01-12 05:25:44 +00:00
Venkatraman Govindaraju cd4d9ac62a [Sparc] Add support for parsing floating point instructions.
llvm-svn: 199033
2014-01-12 04:48:54 +00:00
Saleem Abdulrasool fb3950ec63 ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

llvm-svn: 199032
2014-01-12 04:36:01 +00:00
Jakob Stoklund Olesen e7084a1c5c The SPARCv9 ABI returns a float in %f0.
This is different from the argument passing convention which puts the
first float argument in %f1.

With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...

Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.

llvm-svn: 199028
2014-01-12 04:13:17 +00:00
Joerg Sonnenberger 4bde03023b Typo
llvm-svn: 199027
2014-01-12 03:38:30 +00:00
Joerg Sonnenberger 485f00fe0f Add missing mul aliases for armv4 support. Add checks that armv4 can
assemble the various mul instructions.

llvm-svn: 199026
2014-01-12 03:35:18 +00:00
Hans Wennborg ac114a3ce7 Switch-to-lookup tables: Don't require a result for the default
case when the lookup table doesn't have any holes.

This means we can build a lookup table for switches like this:

  switch (x) {
    case 0: return 1;
    case 1: return 2;
    case 2: return 3;
    case 3: return 4;
    default: exit(1);
  }

The default case doesn't yield a constant result here, but that doesn't matter,
since a default result is only necessary for filling holes in the lookup table,
and this table doesn't have any holes.

This makes us transform 505 more switches in a clang bootstrap, and shaves 164 KB
off the resulting clang binary.

llvm-svn: 199025
2014-01-12 00:44:41 +00:00
Venkatraman Govindaraju a66b314c34 [Sparc] Add missing processor types: v7 and niagara
llvm-svn: 199024
2014-01-11 23:56:13 +00:00
Saleem Abdulrasool 2d48edeca3 ARM IAS: support emitting constant values in target expressions
A 32-bit immediate value can be formed from a constant expression and loaded
into a register.  Add support to emit this into an object file.  Because this
value is a constant, a relocation must *not* be produced for it.

llvm-svn: 199023
2014-01-11 23:03:48 +00:00
Benjamin Kramer c10563d14e Fix broken CHECK lines.
llvm-svn: 199016
2014-01-11 21:06:00 +00:00
Venkatraman Govindaraju 0653218b2b [Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.
llvm-svn: 199014
2014-01-11 19:38:03 +00:00
Chandler Carruth 258dbb3b12 [PM] Actually nest pass managers correctly when parsing the pass
pipeline string. Add tests that cover this now that we have execution
dumping in the pass managers.

llvm-svn: 199005
2014-01-11 12:06:47 +00:00
NAKAMURA Takumi a64d0bccc8 llvm/test/Transforms/SampleProfile/syntax.ll: Eliminate locale-sensitive message check.
llvm-svn: 199000
2014-01-11 09:23:52 +00:00
NAKAMURA Takumi 80a474c1c3 llvm/test/CodeGen/X86/anyregcc.ll: Add explicit -mtriple=x86_64-unknown-unknown.
XMM(s) are really spilling for targeting Win64.

llvm-svn: 198999
2014-01-11 09:23:44 +00:00
Chandler Carruth 66445382ff [PM] Add (very skeletal) support to opt for running the new pass
manager. I cannot emphasize enough that this is a WIP. =] I expect it
to change a great deal as things stabilize, but I think its really
important to get *some* functionality here so that the infrastructure
can be tested more traditionally from the commandline.

The current design is looking something like this:

  ./bin/opt -passes='module(pass_a,pass_b,function(pass_c,pass_d))'

So rather than custom-parsed flags, there is a single flag with a string
argument that is parsed into the pass pipeline structure. This makes it
really easy to have nice structural properties that are very explicit.
There is one obvious and important shortcut. You can start off the
pipeline with a pass, and the minimal context of pass managers will be
built around the entire specified pipeline. This makes the common case
for tests super easy:

  ./bin/opt -passes=instcombine,sroa,gvn

But this won't introduce any of the complexity of the fully inferred old
system -- we only ever do this for the *entire* argument, and we only
look at the first pass. If the other passes don't fit in the pass
manager selected it is a hard error.

The other interesting aspect here is that I'm not relying on any
registration facilities. Such facilities may be unavoidable for
supporting plugins, but I have alternative ideas for plugins that I'd
like to try first. My plan is essentially to build everything without
registration until we hit an absolute requirement.

Instead of registration of pass names, there will be a library dedicated
to parsing pass names and the pass pipeline strings described above.
Currently, this is directly embedded into opt for simplicity as it is
very early, but I plan to eventually pull this into a library that opt,
bugpoint, and even Clang can depend on. It should end up as a good home
for things like the existing PassManagerBuilder as well.

There are a bunch of FIXMEs in the code for the parts of this that are
just stubbed out to make the patch more incremental. A quick list of
what's coming up directly after this:
- Support for function passes and building the structured nesting.
- Support for printing the pass structure, and FileCheck tests of all of
  this code.
- The .def-file based pass name parsing.
- IR priting passes and the corresponding tests.

Some obvious things that I'm not going to do right now, but am
definitely planning on as the pass manager work gets a bit further:
- Pull the parsing into library, including the builders.
- Thread the rest of the target stuff into the new pass manager.
- Wire support for the new pass manager up to llc.
- Plugin support.

Some things that I'd like to have, but are significantly lower on my
priority list. I'll get to these eventually, but they may also be places
where others want to contribute:
- Adding nice error reporting for broken pass pipeline descriptions.
- Typo-correction for pass names.

llvm-svn: 198998
2014-01-11 08:16:35 +00:00
Juergen Ributzka 976d94b834 [anyregcc] Fix callee-save mask for anyregcc
Use separate callee-save masks for XMM and YMM registers for anyregcc on X86 and
select the proper mask depending on the target cpu we compile for.

llvm-svn: 198985
2014-01-11 01:00:27 +00:00
Diego Novillo 9518b63bfc Extend and simplify the sample profile input file.
1- Use the line_iterator class to read profile files.

2- Allow comments in profile file. Lines starting with '#'
   are completely ignored while reading the profile.

3- Add parsing support for discriminators and indirect call samples.

   Our external profiler can emit more profile information that we are
   currently not handling. This patch does not add new functionality to
   support this information, but it allows profile files to provide it.

   I will add actual support later on (for at least one of these
   features, I need support for DWARF discriminators in Clang).

   A sample line may contain the following additional information:

   Discriminator. This is used if the sampled program was compiled with
   DWARF discriminator support
   (http://wiki.dwarfstd.org/index.php?title=Path_Discriminators). This
   is currently only emitted by GCC and we just ignore it.

   Potential call targets and samples. If present, this line contains a
   call instruction. This models both direct and indirect calls. Each
   called target is listed together with the number of samples. For
   example,

                    130: 7  foo:3  bar:2  baz:7

   The above means that at relative line offset 130 there is a call
   instruction that calls one of foo(), bar() and baz(). With baz()
   being the relatively more frequent call target.

   Differential Revision: http://llvm-reviews.chandlerc.com/D2355

4- Simplify format of profile input file.

   This implements earlier suggestions to simplify the format of the
   sample profile file. The symbol table is not necessary and function
   profiles do not need to know the number of samples in advance.

   Differential Revision: http://llvm-reviews.chandlerc.com/D2419

llvm-svn: 198973
2014-01-10 23:23:51 +00:00
Diego Novillo 0accb3d2bc Propagation of profile samples through the CFG.
This adds a propagation heuristic to convert instruction samples
into branch weights. It implements a similar heuristic to the one
implemented by Dehao Chen on GCC.

The propagation proceeds in 3 phases:

1- Assignment of block weights. All the basic blocks in the function
   are initial assigned the same weight as their most frequently
   executed instruction.

2- Creation of equivalence classes. Since samples may be missing from
   blocks, we can fill in the gaps by setting the weights of all the
   blocks in the same equivalence class to the same weight. To compute
   the concept of equivalence, we use dominance and loop information.
   Two blocks B1 and B2 are in the same equivalence class if B1
   dominates B2, B2 post-dominates B1 and both are in the same loop.

3- Propagation of block weights into edges. This uses a simple
   propagation heuristic. The following rules are applied to every
   block B in the CFG:

   - If B has a single predecessor/successor, then the weight
     of that edge is the weight of the block.

   - If all the edges are known except one, and the weight of the
     block is already known, the weight of the unknown edge will
     be the weight of the block minus the sum of all the known
     edges. If the sum of all the known edges is larger than B's weight,
     we set the unknown edge weight to zero.

   - If there is a self-referential edge, and the weight of the block is
     known, the weight for that edge is set to the weight of the block
     minus the weight of the other incoming edges to that block (if
     known).

Since this propagation is not guaranteed to finalize for every CFG, we
only allow it to proceed for a limited number of iterations (controlled
by -sample-profile-max-propagate-iterations). It currently uses the same
GCC default of 100.

Before propagation starts, the pass builds (for each block) a list of
unique predecessors and successors. This is necessary to handle
identical edges in multiway branches. Since we visit all blocks and all
edges of the CFG, it is cleaner to build these lists once at the start
of the pass.

Finally, the patch fixes the computation of relative line locations.
The profiler emits lines relative to the function header. To discover
it, we traverse the compilation unit looking for the subprogram
corresponding to the function. The line number of that subprogram is the
line where the function begins. That becomes line zero for all the
relative locations.

llvm-svn: 198972
2014-01-10 23:23:46 +00:00
Arnold Schwaighofer c2e9d759f2 LoopVectorizer: Handle strided memory accesses by versioning
for (i = 0; i < N; ++i)
   A[i * Stride1] += B[i * Stride2];

We take loops like this and check that the symbolic strides 'Strided1/2' are one
and drop to the scalar loop if they are not.

This is currently disabled by default and hidden behind the flag
'enable-mem-access-versioning'.

radar://13075509

llvm-svn: 198950
2014-01-10 18:20:32 +00:00
Artyom Skrobov 4e62c0b2b2 Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M
llvm-svn: 198946
2014-01-10 16:49:49 +00:00
Artyom Skrobov 4d91d944ae Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
llvm-svn: 198945
2014-01-10 16:42:55 +00:00
Saleem Abdulrasool b16c09f241 ARM: fix regression caused by r198914
The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

llvm-svn: 198944
2014-01-10 16:22:47 +00:00
Kristof Beyls 58306ad903 Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux.
llvm-svn: 198937
2014-01-10 13:41:49 +00:00
NAKAMURA Takumi d38ac74662 llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Remove "REQUIRES:shell". This doesn't depend on shell's behavior.
llvm-svn: 198931
2014-01-10 10:38:52 +00:00
NAKAMURA Takumi 566080cc80 llvm/test/ExecutionEngine/MCJIT/lit.local.cfg: Add "AMD64" in the host_arch list.
FIXME: We should not take CMake's ${CMAKE_SYSTEM_PROCESSOR}...
llvm-svn: 198930
2014-01-10 10:38:46 +00:00
NAKAMURA Takumi 52f9d3818b llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Fix not to use %t.cachedir/%p.
%p is like X:\foo\bar.

llvm-svn: 198926
2014-01-10 10:38:23 +00:00
Saleem Abdulrasool 435f45653a ARM IAS: support #:{lower,upper}16: for GNU compatibility
The GNU assembler supports prefixing the expression with a '#' to indiciate that
the value that is being moved is infact a constant.  This improves the
compatibility of the integrated assembler's parser for this.

llvm-svn: 198916
2014-01-10 04:38:40 +00:00
Saleem Abdulrasool e6e6d71477 ARM IAS: support GNU extension for ldrd, strd
The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

llvm-svn: 198915
2014-01-10 04:38:35 +00:00
Saleem Abdulrasool 5bfefb6a8f ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

llvm-svn: 198914
2014-01-10 04:38:31 +00:00
Venkatraman Govindaraju ad40dfcb4b [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated.
llvm-svn: 198910
2014-01-10 02:55:27 +00:00
Venkatraman Govindaraju 0d288d3105 [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.
llvm-svn: 198909
2014-01-10 01:48:17 +00:00
David Blaikie 15ed5ebfc5 Revert "Revert r198851, "Prototype of skeleton type units for fission""
This reverts commit r198865 which reverts r198851.

ASan identified a use-of-uninitialized of the DwarfTypeUnit::Ty variable
in skeleton type units.

llvm-svn: 198908
2014-01-10 01:38:41 +00:00
Kevin Enderby 9bd296ab55 Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions that
branch to the next instruction.  This can not be encoded but can be
turned into a NOP.

rdar://15062072

llvm-svn: 198904
2014-01-10 00:43:32 +00:00