6e1faaf886
Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc.
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llvm-svn: 200091
2014-01-25 17:40:33 +00:00
336e1f1179
Fix typo in commment tyep->type.
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llvm-svn: 200089
2014-01-25 17:34:23 +00:00
5f730e8ef1
Use isConcrete and getConcrete instead of using TypeVec directly.
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llvm-svn: 200071
2014-01-25 05:33:48 +00:00
6dbcb945a2
Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar.
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llvm-svn: 200070
2014-01-25 05:17:38 +00:00
3f9978e65a
Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036.
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llvm-svn: 200037
2014-01-24 20:51:32 +00:00
8561de90d7
Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).
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llvm-svn: 200036
2014-01-24 20:50:47 +00:00
cb40291100
Fix known typos
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Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
2014-01-24 17:20:08 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
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llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
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llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
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llvm-svn: 199803
2014-01-22 15:08:08 +00:00
a2c60197bf
Use ArrayRef to simplify some code.
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llvm-svn: 199712
2014-01-21 07:20:05 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
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The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
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llvm-svn: 199364
2014-01-16 07:36:58 +00:00
317e2c499d
replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h>
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llvm-svn: 199303
2014-01-15 07:59:37 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
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llvm-svn: 199295
2014-01-15 05:02:02 +00:00
06234ec147
Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
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promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).
Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.
llvm-svn: 199252
2014-01-14 19:56:36 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
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llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
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This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
b19c9dc1a1
AVX-512: Embedded Rounding Control - encoding and printing
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Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.
llvm-svn: 199102
2014-01-13 12:55:03 +00:00
9dc6df5744
Constant propagate MachineInstrClassName.
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llvm-svn: 198969
2014-01-10 22:59:49 +00:00
f581314932
All backends use MC now.
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llvm-svn: 198959
2014-01-10 21:49:27 +00:00
a6afef7a51
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off
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llvm-svn: 198922
2014-01-10 08:05:42 +00:00
2a2a354ee9
Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"
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To declare or define reserved identifers is undefined behaviour in standard
C++. This needs to be addressed in compiler-rt before it can be used in LLVM.
See the list discussion for details.
This reverts commit r198858.
llvm-svn: 198884
2014-01-09 19:40:55 +00:00
bc60254543
Disable LeakSanitizer in TableGen binaries, see PR18325
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llvm-svn: 198858
2014-01-09 09:26:26 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
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It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
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llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
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llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
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llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
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llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
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llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
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llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
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llvm-svn: 198543
2014-01-05 04:17:28 +00:00
5999d47538
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
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llvm-svn: 198530
2014-01-05 01:35:51 +00:00
7d4e01cdcb
Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time.
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llvm-svn: 198529
2014-01-05 01:34:12 +00:00
bc281ad8c1
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
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llvm-svn: 198515
2014-01-04 22:29:41 +00:00
1da8582322
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
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llvm-svn: 198475
2014-01-04 05:09:27 +00:00
49f1c2a733
[TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResults
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A ValueType in a pattern dag is a type cast, and GetNumNodeResults should
handle it (the type cast has only one result).
This comes up, for example, during the type checking of pattern fragments, for
example, AArch64's Neon_combine_2d fragment is:
dag Operands = (ops node:$Rm, node:$Rn);
dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn)));
llvm-svn: 198347
2014-01-02 20:47:05 +00:00
66c20f344e
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
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llvm-svn: 198336
2014-01-02 19:12:10 +00:00
fae226c67e
Remove unused HasFROperands field from disassembler.
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llvm-svn: 198332
2014-01-02 18:44:21 +00:00
eabdbcb8a9
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
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llvm-svn: 198327
2014-01-02 18:20:48 +00:00
a941d2b08e
Remove unnecessary stirng comparison from disassembler.
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llvm-svn: 198325
2014-01-02 17:41:40 +00:00
9dd48c8ed4
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
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llvm-svn: 198323
2014-01-02 17:28:14 +00:00
83b7e24b76
Remove unused function argument.
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llvm-svn: 198291
2014-01-02 03:58:45 +00:00
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
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llvm-svn: 198284
2014-01-01 21:52:57 +00:00
9155118602
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
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llvm-svn: 198278
2014-01-01 15:29:32 +00:00
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
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Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
623b0d64b3
Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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llvm-svn: 198276
2014-01-01 14:22:37 +00:00
e98c8cb9f0
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
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llvm-svn: 198265
2013-12-31 17:21:44 +00:00
0e21bca6dd
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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llvm-svn: 198238
2013-12-30 19:16:48 +00:00
6d776e2660
Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change.
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llvm-svn: 198226
2013-12-30 17:37:10 +00:00
Craig Topper