7867793aff
Add new TargetLowering code to provide the final register type that an
...
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
llvm-svn: 37781
2007-06-28 23:29:44 +00:00
df0c705d7d
If a livein is not used in the block. It's live through.
...
llvm-svn: 37764
2007-06-27 18:47:28 +00:00
77f541ddfd
Partial fix for PR1502: If a EH register is needed in a successor of landing pad, add it as livein to all the blocks in the paths between the landing pad and the specified block.
...
llvm-svn: 37763
2007-06-27 18:45:32 +00:00
3b62d7265d
Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
...
llvm-svn: 37758
2007-06-27 16:08:04 +00:00
7139a48057
Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
...
to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.
llvm-svn: 37755
2007-06-27 14:34:07 +00:00
f4e86da3a6
Make the comment for ScalarizeVectorOp mention that it is only for use
...
with single-element vectors.
llvm-svn: 37752
2007-06-27 14:06:22 +00:00
95759c0e78
ok, this is something of a dirty hack, but it seems to work. (fixes e.g.
...
the SPASS miscompilation)
llvm-svn: 37750
2007-06-27 09:01:14 +00:00
89183dcc14
ok, this much doesn't seem to bork anything
...
llvm-svn: 37749
2007-06-27 08:31:07 +00:00
a415dcaa2a
revert evan's fixes (and my doofusness) since they had a huge code
...
quality hit. will look at this soon.
llvm-svn: 37748
2007-06-27 08:11:59 +00:00
540d329542
pull evan's fixes - should help the nightly tester (but there are still
...
some issues)
llvm-svn: 37747
2007-06-27 07:07:13 +00:00
e66f822ecc
Replace std::set with SmallPtrSet.
...
llvm-svn: 37746
2007-06-27 05:23:00 +00:00
6cf1371456
Fix an obvious bug. Old code only worked for the entry block.
...
llvm-svn: 37743
2007-06-27 01:16:36 +00:00
4bf87f1f44
Correctly handle implcit def / use operands.
...
llvm-svn: 37740
2007-06-26 21:05:13 +00:00
d8417d9199
Properly handle kills of a physical register which has sub-registers that are read by later instructions.
...
llvm-svn: 37739
2007-06-26 21:03:35 +00:00
f4dc5b26e2
tidy this file up a bit
...
llvm-svn: 37725
2007-06-26 00:21:58 +00:00
77416383e8
A bunch of fixes to the BigBlock allocator improve compile-time by ~20%
...
and code quality by ~2% on my tests.
A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.
llvm-svn: 37724
2007-06-25 23:46:54 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
81a752aa95
check in the BigBlock local register allocator
...
llvm-svn: 37703
2007-06-22 08:27:12 +00:00
e3c4419953
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
...
llvm-svn: 37701
2007-06-22 01:35:51 +00:00
8e8d34b220
Tidy up ValueType names in comments.
...
llvm-svn: 37688
2007-06-21 14:48:26 +00:00
04deef3a49
Rename TargetLowering::getNumElements and friends to
...
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
llvm-svn: 37687
2007-06-21 14:42:22 +00:00
aa5f5d960d
Xforms:
...
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
llvm-svn: 37685
2007-06-21 07:39:16 +00:00
a955c02c9b
Avoid if-converting simple block that ends with unconditional branch or fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.
...
llvm-svn: 37660
2007-06-19 21:45:13 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
...
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
37228f6ce5
document and hide two options.
...
llvm-svn: 37651
2007-06-19 05:47:49 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
26be02febf
add isVarArg to CCState
...
llvm-svn: 37640
2007-06-19 00:11:09 +00:00
0598b2d5eb
Fix some fragile code wrt CFG edge updating.
...
llvm-svn: 37634
2007-06-18 22:44:57 +00:00
2afd702c20
Move CorrectExtraCFGEdges() from BranchFolding.cpp to a MachineBasicBlock method.
...
llvm-svn: 37633
2007-06-18 22:43:58 +00:00
e31adc8ab9
make ComputeTopDownOrdering significantly faster and use less stack space
...
by making it non-recursive
llvm-svn: 37629
2007-06-18 21:28:10 +00:00
8c7333266c
Make chain dependencies blue, in addition to being dashed.
...
llvm-svn: 37626
2007-06-18 15:30:16 +00:00
51eb2c3bbe
Properly remove duplicate instructions as result of diamond if-conversion. Other bug fixes.
...
llvm-svn: 37623
2007-06-18 08:37:25 +00:00
3a51c854d0
Really turn if-converter loose:
...
1. Consider all possible ifcvt cases at once. No longer restricted to bottom
up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.
llvm-svn: 37613
2007-06-16 09:34:52 +00:00
e199f97fa8
Codegen support (stripped out) for the annotate attribute.
...
llvm-svn: 37608
2007-06-15 22:26:58 +00:00
23402fcaef
Not every predicable block can be safely duplicated.
...
llvm-svn: 37607
2007-06-15 21:18:05 +00:00
f852e339b6
Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
...
for tied register constraints.
llvm-svn: 37601
2007-06-15 19:11:01 +00:00
234a90e83e
MachineInstr::isPredicable() is no longer needed.
...
llvm-svn: 37599
2007-06-15 19:06:07 +00:00
92bf2c628c
Workaround for PR1508.
...
llvm-svn: 37597
2007-06-15 19:04:19 +00:00
cd5f5e3ecd
Extra edges are deleted later if needed.
...
llvm-svn: 37593
2007-06-15 17:34:48 +00:00
92fb5453c3
Allow small blocks to be duplicated to enable if-conversion.
...
llvm-svn: 37590
2007-06-15 07:36:12 +00:00
add977670f
No really, clear predcessors states.
...
llvm-svn: 37581
2007-06-14 23:34:09 +00:00
9fc56c079d
If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.
...
llvm-svn: 37580
2007-06-14 23:13:19 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
e08f0eefa6
Fix typo.
...
llvm-svn: 37577
2007-06-14 21:26:08 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
1e6f08b2a2
Fix some stupid bugs that have effectively disabled if-conversion.
...
llvm-svn: 37575
2007-06-14 20:28:52 +00:00
7413736a7e
Only correctly lower exception handing intrinsics if exception handling is
...
turned on. Likewise for scanning of invokes to mark landing pads.
llvm-svn: 37570
2007-06-13 16:53:21 +00:00
26455c4ae0
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
...
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
llvm-svn: 37569
2007-06-13 15:12:02 +00:00
cbd51c8b60
When creating CopyFromReg nodes, always use legal types. And use the
...
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
llvm-svn: 37568
2007-06-13 14:55:16 +00:00
97f7236e70
The fix that was applied for PR1224 stops the compiler
...
crashing but breaks exception handling. The problem
described in PR1224 is that invoke is a terminator that
can produce a value. The value may be needed in other
blocks. The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available. The fix that was applied was to do invoke
lowering earlier, before writing values to registers.
The problem this causes is that the code to copy values
to registers can be output after the invoke call. If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute. If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.
So revert the original fix and simply skip invoke values
in the general copying to registers code. Instead copy
the invoke value to a register in the invoke lowering code.
llvm-svn: 37567
2007-06-13 05:51:31 +00:00
cbaaff58bf
Typo
...
llvm-svn: 37566
2007-06-13 00:04:00 +00:00
9acfa7b063
Now if-converting all 4 variants of triangles.
...
llvm-svn: 37565
2007-06-12 23:54:05 +00:00
4c2f003971
Fix a typo in bswap lowering.
...
llvm-svn: 37544
2007-06-11 23:16:16 +00:00
4dd31a7b1b
Restructure code to reduce ifcvt compile time cost.
...
llvm-svn: 37543
2007-06-11 22:26:22 +00:00
14b62a553e
Fix the build.
...
llvm-svn: 37537
2007-06-10 00:19:17 +00:00
2117d1f20e
Don't change CFG during analysis stage. Do so during ifcvt and invalidate predecessors accordingly.
...
llvm-svn: 37531
2007-06-09 01:03:43 +00:00
288f1545a6
Carefully remove extraneous CFG edges after each ifcvt.
...
llvm-svn: 37529
2007-06-08 22:01:07 +00:00
df1a42935b
Correct transfer predicate information.
...
llvm-svn: 37524
2007-06-08 19:17:12 +00:00
e93ccc013f
Hidden options to help debugging ifcvt issues.
...
llvm-svn: 37523
2007-06-08 19:10:51 +00:00
02f6e9b621
Factor live variable analysis so it does not do register coalescing
...
simultaneously. Move that pass to SimpleRegisterCoalescing.
This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.
llvm-svn: 37520
2007-06-08 17:18:56 +00:00
7783f82e21
Allow more cmp / bcc to be predicated; clean up triangle ifcvt checking code.
...
llvm-svn: 37518
2007-06-08 09:36:04 +00:00
dc8fc1550e
Use more realistically sized vectors. Reserve capacity if we know in advance
...
how much will be used.
llvm-svn: 37515
2007-06-08 08:59:11 +00:00
86798e5e11
Make throttle a hidden parameter, per review.
...
llvm-svn: 37511
2007-06-08 01:08:52 +00:00
52fcf022f7
Throttle tail merging; handling blocks with large numbers of predecessors
...
is too slow.
llvm-svn: 37509
2007-06-08 00:34:27 +00:00
1236ef7bcc
Only remove the edge from entry to false if false block is merged.
...
llvm-svn: 37503
2007-06-07 22:31:28 +00:00
9a4d987a5f
Do not change the size of function arguments. PR 1489.
...
llvm-svn: 37496
2007-06-07 21:07:15 +00:00
d3f3f0adad
ifcvt a triangle: don't merge ifcvt block with rejoin block if it can fall through to it. If merged, the resulting block is not a candidate for iterative ifcvting since it contains both predicated and non-predicated code.
...
llvm-svn: 37487
2007-06-07 08:13:00 +00:00
be9859eea2
Lots of bug fixes. Now finally in a reasonable state.
...
llvm-svn: 37485
2007-06-07 02:12:15 +00:00
cfb6f40424
Quick patch to fix the build, based on what it appears Evan meant to write.
...
Evan, please check that this is in fact correct.
llvm-svn: 37471
2007-06-06 16:22:00 +00:00
29d1dc6f1a
Fold the exception actions table harder: if two typeid lists start the
...
same, only output one copy of the common part.
llvm-svn: 37470
2007-06-06 15:37:31 +00:00
9030b98aca
Lots of bug fixes.
...
llvm-svn: 37467
2007-06-06 10:16:17 +00:00
61166501a1
Additional fix for PR1422: make sure the landing pad label is placed in the
...
correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.
llvm-svn: 37463
2007-06-06 10:05:18 +00:00
e4ec918be0
If a unconditional branch is added to branch to the false path during ifcvt, the predicated block cannot be iteratively ifcvted.
...
llvm-svn: 37456
2007-06-06 02:08:52 +00:00
b30a89457c
Minor statistics counting bug.
...
llvm-svn: 37451
2007-06-06 01:12:44 +00:00
30565998bb
Fix a couple of typos and be smarter about order of blocks when ifcvt a diamond.
...
llvm-svn: 37449
2007-06-06 00:57:55 +00:00
7948422b78
Fix diamond shape ifcvt bugs.
...
llvm-svn: 37444
2007-06-05 23:46:14 +00:00
c1a0b8ce1d
ReplaceUsesOfBlockWith() can modify the predecessors list.
...
llvm-svn: 37441
2007-06-05 22:03:53 +00:00
3e5bf0827c
Do not ifcvt if either true / false path is a backedge. Not profitable in almost all cases.
...
llvm-svn: 37440
2007-06-05 20:38:42 +00:00
2c1acd6d9e
I had a senior moment.
...
llvm-svn: 37433
2007-06-05 07:05:25 +00:00
6e4babe8cc
If the predicated block requires an early exit, end the block there and add a unconditional branch to false block. AnalyzeBranch() does not understand early exits.
...
llvm-svn: 37430
2007-06-05 01:31:40 +00:00
17aad8164e
Fix some subtle bugs: bug during succeessor copying; incorrectly updating states of ifcvted blocks.
...
llvm-svn: 37429
2007-06-05 00:07:37 +00:00
0558dda319
Tail merging wasn't working for predecessors of landing pads. PR 1496.
...
llvm-svn: 37427
2007-06-04 23:52:54 +00:00
53ce7de03b
Global ctors / dtors alignment shouldn't be hard-coded at 4. e.g. It could be 8 for 64-bit targets.
...
llvm-svn: 37421
2007-06-04 20:39:18 +00:00
91233153bf
Forgot to check for if iterator reached the end.
...
llvm-svn: 37420
2007-06-04 20:33:36 +00:00
b4c2690446
Pass the DAG to SDNode::dump to let it do more detailed dumps in some cases.
...
llvm-svn: 37413
2007-06-04 16:17:33 +00:00
92a7f3a65e
Resolve implicit alignment before computing the FoldingSet information so
...
that the CSE map always contains explicit alignment information. This allows
more loads to be CSE'd when there is a mix of explicit-alignment loads and
implicit-alignment loads.
Also, in SelectionDAG::FindModifiedNodeSlot, add the operands to the
FoldingSetNodeID before the load/store information instead of after, so
that it matches what is done elsewhere.
llvm-svn: 37411
2007-06-04 15:49:41 +00:00
312b723af2
Let IfConverter loose. Allow more aggressive subsumptions; reorder basic blocks to expose more ifcvt opportunities; code clean up and fixes.
...
llvm-svn: 37409
2007-06-04 06:47:22 +00:00
df75785594
Move ReplaceUsesOfBlockWith() out of BranchFolding into a MachineBasicBlock general facility.
...
llvm-svn: 37408
2007-06-04 06:44:01 +00:00
f708f73a1b
The semantics of invoke require that we always jump to the unwind block
...
(landing pad) when an exception unwinds through the call. This doesn't
quite match the way the dwarf unwinder works: by default it only jumps to
the landing pad if the catch or filter specification matches, and otherwise
it keeps on unwinding. There are two ways of specifying to the unwinder
that it should "always" (more on why there are quotes here later) jump to
the landing pad: follow the specification by a 0 typeid, or follow it by
the typeid for the NULL typeinfo. GCC does the first, and this patch makes
LLVM do the same as gcc. However there is a problem: the unwinder performs
optimizations based on C++ semantics (it only expects destructors to be
run if the 0 typeid fires - known as "cleanups"), meaning it assumes that no
exceptions will be raised and that the raised exception will be reraised
at the end of the cleanup code. So if someone writes their own LLVM code
using the exception intrinsics they will get a nasty surprise if they don't
follow these rules. The other possibility of using the typeid corresponding
to NULL (catch-all) causes the unwinder to make no assumptions, so this is
probably what we should use in the long-run. However since we are still
having trouble getting exception handling working properly, for the moment
it seems best to closely imitate GCC.
llvm-svn: 37399
2007-06-02 17:16:06 +00:00
c063f5f362
Integrate exception filter support and exception catch support. This
...
simplifies the code in DwarfWriter, allows for multiple filters and
makes it trivial to specify filters accompanied by cleanups or catch-all
specifications (see next patch). What a deal! Patch blessed by Anton.
llvm-svn: 37398
2007-06-02 16:53:42 +00:00
0a0ae932ca
Make LowerCTPOP() support arbitrary bitwidth integer type.
...
llvm-svn: 37397
2007-06-02 04:10:33 +00:00
6e7cdce773
Fix CorrectExtraCFGEdges to allow for multiple LandingPad targets.
...
llvm-svn: 37394
2007-06-02 00:08:15 +00:00
9746e3a22b
Fancier algorithm in tail-merge comment implemented, so remove comment.
...
llvm-svn: 37393
2007-06-01 23:04:28 +00:00
3c0a13762d
Implement smarter algorithm for choosing which blocks to tail-merge.
...
See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark. I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.
llvm-svn: 37392
2007-06-01 23:02:45 +00:00
4dcf1e8582
Correctly mark early-exit on the false path.
...
llvm-svn: 37387
2007-06-01 20:29:21 +00:00
706421e712
Since TypeInfos are passed as i8 pointers, a NULL TypeInfo should be passed
...
as a null i8 pointer not as a 0 i32.
llvm-svn: 37383
2007-06-01 08:18:30 +00:00
6a2cf070cc
Ifcvt triangle: don't ifcvt 'true' BB if it has other predecessors; don't merge 'false' BB if it has other predecessors.
...
llvm-svn: 37382
2007-06-01 07:41:07 +00:00
95c7917d92
Remove a bogus check. Even terminators in a ifcvt need to be predicated. Unconditional branches can usually be converted to conditional ones.
...
llvm-svn: 37380
2007-06-01 00:55:26 +00:00
20e05997f5
Allow multiple ifcvt candidates to share children blocks; add some debugging code.
...
llvm-svn: 37379
2007-06-01 00:12:12 +00:00
1a401e68a8
Arrange for only 1 of multiple branches to landing pad to be kept.
...
Do not remove empty landing pads (EH table needs to be updated)
llvm-svn: 37375
2007-05-31 21:54:00 +00:00
e6ccb6c5ed
Fix a typo.
...
llvm-svn: 37374
2007-05-31 20:53:33 +00:00
3e3ff30aa2
Fix the asmprinter so that a globalvalue can specify an explicit alignment
...
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
llvm-svn: 37373
2007-05-31 18:57:45 +00:00
5b0757a401
Fix PR1424.
...
When a function has FP, the register scavenging spill slot offset already
was calculated.
llvm-svn: 37371
2007-05-31 18:27:58 +00:00
905a8f4940
Change traversal order to bottom up in preparation for more aggressive if-conversion.
...
llvm-svn: 37365
2007-05-30 19:49:19 +00:00
397c4d9ef6
Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.
...
llvm-svn: 37362
2007-05-30 16:30:06 +00:00
d14ad078c6
Changed per review comment.
...
llvm-svn: 37355
2007-05-30 00:32:01 +00:00
a69ebdbebc
Make stable_sort in tail merging actually be stable (it never was, but didn't
...
matter until my last change). Reenable tail merging by default.
llvm-svn: 37354
2007-05-29 23:47:50 +00:00
20f7d30f92
Don't merge in tail block of a diamond if it has more than one predecessors after if-conversion.
...
llvm-svn: 37353
2007-05-29 23:37:20 +00:00
c2237ce217
If there is an empty block between a source and its successor block, it still requires a unconditional branch.
...
llvm-svn: 37344
2007-05-29 22:31:16 +00:00
5983bdbb2c
Add missing const qualifiers.
...
llvm-svn: 37341
2007-05-29 18:35:22 +00:00
d7dc1ed64c
Correct the logic in LowerPartSet which cleared the bits from 0 to low-1.
...
llvm-svn: 37331
2007-05-26 03:43:13 +00:00
4698083b96
tighten up recursion depth again
...
llvm-svn: 37330
2007-05-25 02:19:06 +00:00
13f5f7df95
Silly boog.
...
llvm-svn: 37328
2007-05-25 00:59:01 +00:00
1409b6a59b
Blocks that cond-br and uncond-br/fallthrough to same block should have
...
only one successor.
llvm-svn: 37324
2007-05-24 18:31:55 +00:00
1af8c870c7
Fix for PR1444: do not create two successors to the same block.
...
Temporarily, this breaks CodeGen/Generic/2006-02-12-InsertLibraryCall.ll
by exposing an unrelated latent problem; working on that.
llvm-svn: 37323
2007-05-24 17:39:32 +00:00
30978078bf
Minor comment cleanups.
...
llvm-svn: 37321
2007-05-24 14:36:04 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
...
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
a4d187b8ce
Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.
...
llvm-svn: 37318
2007-05-24 02:35:39 +00:00
f4a77d2481
Two tail merging improvements:
...
When considering blocks with more than 2 predecessors, merge the block with
the largest number of matching insns, rather than the first block found.
Considering that 1 matching insn is enough to show a win for candidates that
already end with a branch.
llvm-svn: 37315
2007-05-23 21:07:20 +00:00
3b327826db
Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439
...
llvm-svn: 37311
2007-05-23 11:08:31 +00:00
6509c0673f
prevent exponential recursion in isNegatibleForFree
...
llvm-svn: 37310
2007-05-23 07:35:22 +00:00
d0e669199b
Preliminary iterative if-conversion support.
...
llvm-svn: 37309
2007-05-23 07:23:16 +00:00
f9cbdc676c
name change requested by review of previous patch
...
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
0ae7eb5e7c
Silence a warning.
...
llvm-svn: 37288
2007-05-22 18:13:40 +00:00
82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
...
for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
e26c0916a3
If-convert early exit blocks (returns, etc.); bug fixes, etc.
...
llvm-svn: 37270
2007-05-21 22:22:58 +00:00
34e82a4508
Only emit one entry in the exception action table for each action, even if
...
it occurs for multiple landing pads.
llvm-svn: 37267
2007-05-21 18:50:28 +00:00
1fa8276e70
same patch as the previous one, but the symmetric case
...
llvm-svn: 37249
2007-05-19 00:46:51 +00:00
b08cbbd737
Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (in
...
this case, the xform introduces an extra operation). This compiles
PowerPC/compare-duplicate.ll into:
_test:
subf r2, r3, r4
cmplw cr0, r2, r3
bne cr0, LBB1_2 ;F
instead of:
_test:
slwi r2, r3, 1
subf r3, r3, r4
cmplw cr0, r4, r2
bne cr0, LBB1_2 ;F
This is target independent of course.
llvm-svn: 37246
2007-05-19 00:43:44 +00:00
018cffbca4
Clean up.
...
llvm-svn: 37237
2007-05-18 19:32:08 +00:00
faaf716540
Change to depth-first traversal.
...
llvm-svn: 37236
2007-05-18 19:26:33 +00:00
dafda82755
Document an inefficiency in tail merging.
...
llvm-svn: 37235
2007-05-18 18:46:40 +00:00
b539df3389
Qualify calls to getTypeForValueType with MVT:: too.
...
llvm-svn: 37233
2007-05-18 18:41:29 +00:00
2e82cefd24
Some restructuring in preparation for most aggressive if-conversion.
...
llvm-svn: 37231
2007-05-18 18:14:37 +00:00
1796f1f8e9
Qualify several calls to functions in the MVT namespace, for consistency.
...
llvm-svn: 37230
2007-05-18 17:52:13 +00:00
f25d3a5d73
Watch out for blocks that end with a return.
...
llvm-svn: 37227
2007-05-18 17:06:53 +00:00
478b805956
If true / false blocks fallthrough before ifcvt, add unconditional branches to ifcvt'd block.
...
llvm-svn: 37200
2007-05-18 01:55:58 +00:00
f8956178af
Remove some unneeded branches. (spotted by Evan, thanks)
...
llvm-svn: 37198
2007-05-18 01:28:58 +00:00
0f745da4fe
Make use of target specific block size limits; bug fixes.
...
llvm-svn: 37195
2007-05-18 00:20:58 +00:00
a92b2b38ff
Move isSuccessor() offline, change it to use std::find.
...
llvm-svn: 37190
2007-05-17 23:58:53 +00:00
0184f88deb
disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for
...
i128 integers. The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.
llvm-svn: 37169
2007-05-17 18:19:23 +00:00
2135bc08d6
add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets
...
llvm-svn: 37168
2007-05-17 18:15:41 +00:00
429178d727
Add target hook to specify block size limit for if-conversion.
...
llvm-svn: 37134
2007-05-16 23:45:53 +00:00
7a6c175e7a
Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
...
llvm-svn: 37130
2007-05-16 22:45:30 +00:00
af71610429
isBlockPredicable() always ignore terminal instructions; add comments.
...
llvm-svn: 37126
2007-05-16 21:54:37 +00:00
5ea933a009
Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.
...
llvm-svn: 37121
2007-05-16 20:56:08 +00:00
59ae77486c
Output exception call-sites in address order, as required by the unwinding
...
runtime.
llvm-svn: 37104
2007-05-16 12:12:23 +00:00
48fb92f75d
Use a ptr set instead of a linear search to unique TokenFactor operands.
...
This fixes PR1423
llvm-svn: 37102
2007-05-16 06:37:59 +00:00
35fc2119b0
Devang points out that we need an assertion here.
...
llvm-svn: 37097
2007-05-16 05:11:10 +00:00
288f133c71
Bug fix: should check ABI alignment, not pref. alignment.
...
llvm-svn: 37094
2007-05-16 02:04:50 +00:00
f5e53a58db
Initial commit of (very basic) if converter.
...
llvm-svn: 37092
2007-05-16 02:00:57 +00:00
420a85d0cf
Remove extra CFG edges before doing these passes; it makes them happier.
...
llvm-svn: 37089
2007-05-15 21:19:17 +00:00
3f142cbca2
Fix an infinite recursion in GetNegatedExpression.
...
llvm-svn: 37086
2007-05-15 17:05:43 +00:00
750e8c5d4d
The index into the actions table is a ULEB128 not a SLEB128.
...
llvm-svn: 37084
2007-05-15 13:54:14 +00:00
daed139420
Un-brain-dead-ify the lowering of part set for the reverse case.
...
llvm-svn: 37071
2007-05-15 02:26:52 +00:00
c7596efdad
Fix some subtle issues handling immediate values. This fixes
...
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
llvm-svn: 37069
2007-05-15 01:33:58 +00:00
4d728b0419
Added getNumExplicitOperands and findFirstPredOperand.
...
llvm-svn: 37064
2007-05-15 01:26:09 +00:00
e49c974a7c
implement a simple fneg optimization/propagation thing. This compiles:
...
CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
llvm-svn: 37054
2007-05-14 22:04:50 +00:00
e1595b6859
Only worry about intervening kill if there are more than one live ranges in the interval.
...
llvm-svn: 37052
2007-05-14 21:23:51 +00:00
c690cba7d9
Fix for PR1406:
...
v1 =
r2 = move v1
= op r2<kill>
...
r2 = move v1
= op r2<kill>
Clear the first r2 kill if v1 and r2 are joined.
llvm-svn: 37050
2007-05-14 21:10:05 +00:00
fc2377d4ed
When marking a register as being implicitly defined, make sure to clear its partial use info as well.
...
llvm-svn: 37046
2007-05-14 20:39:18 +00:00
764ae2a21b
Give names to the final result values of the part_set computations. This
...
just aids in readability and debugability of the output. No functional change.
llvm-svn: 37037
2007-05-14 17:21:17 +00:00
1ee0c8d563
Emit function debug frames in one atom. This will prevent us from generating incorrect assembler in case of both
...
debug information & exception information presented.
llvm-svn: 37019
2007-05-13 17:30:11 +00:00
bbaf55448b
Emit multiple common EH frames for multiple (including blank) personality
...
functions. This partly fixes PR1414: now we're restricted only to one
personality function per eh frame, not per module. Further work on
"multiple personalities" topic needs representative example.
llvm-svn: 37018
2007-05-13 15:42:26 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
bf283708f7
Get the size of auto arrays right, regardless of its changing size.
...
llvm-svn: 37006
2007-05-12 11:07:40 +00:00
79a71ec3ad
Fix http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070507/049516.html
...
llvm-svn: 36998
2007-05-11 23:14:43 +00:00
67286b1266
Perform correct actions numbers/sizes computation
...
llvm-svn: 36988
2007-05-11 08:47:35 +00:00
00d02442b0
Fix action No calculation in multiple-invoke-one-LP mode
...
llvm-svn: 36987
2007-05-11 08:23:57 +00:00
cc8f571bc8
Do not generate branches to entry block. This fixes several test suite
...
failures on PPC (can happen only when prologue code is null)
llvm-svn: 36979
2007-05-10 23:59:23 +00:00
ee02c7d2fb
Ooops. Some debugging stuff :)
...
llvm-svn: 36978
2007-05-10 22:38:46 +00:00
96142de3f0
Allow multiple invokes per landing pad. This (probably) fixes PR1410.
...
llvm-svn: 36977
2007-05-10 22:34:59 +00:00
b43fe52136
Later computations assume we are aligned at this point.
...
llvm-svn: 36975
2007-05-10 18:40:24 +00:00
ed5dad4306
TypeIds are indexed by j, not i
...
llvm-svn: 36974
2007-05-10 15:10:34 +00:00
6e16d09252
Make tail merging handle many more cases (all it can, I think).
...
llvm-svn: 36966
2007-05-10 01:01:49 +00:00
f325c2a65e
Can't fold the bit_convert is the store is a truncating store.
...
llvm-svn: 36962
2007-05-09 21:49:47 +00:00
192d09c2d9
Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
...
fixes PR1403.
llvm-svn: 36959
2007-05-09 20:07:08 +00:00
31fd60ba0c
Change names from RA to something unique to get rid of naming conflicts with
...
certain linkers...
llvm-svn: 36944
2007-05-08 19:02:46 +00:00
9e17872c1d
Eliminate MarkVirtRegAliveInBlock recursion.
...
llvm-svn: 36943
2007-05-08 19:00:00 +00:00
562e45692e
Forgot a check.
...
llvm-svn: 36910
2007-05-07 21:36:06 +00:00
a4cf58a103
Enable a couple of xforms:
...
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
llvm-svn: 36908
2007-05-07 21:27:48 +00:00
9a25b3afcd
Handle some non-exit blocks in tail merging.
...
llvm-svn: 36907
2007-05-07 20:57:21 +00:00
671e8c4444
Parameter attributes on invoke calls were being lost due to the wrong
...
attribute index being used. Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him. This is PR1398.
llvm-svn: 36906
2007-05-07 20:49:28 +00:00
a8fd7fdc25
Detabify
...
llvm-svn: 36891
2007-05-06 20:14:21 +00:00
e7da2d6ac3
Fix typo in comment.
...
llvm-svn: 36873
2007-05-06 13:37:16 +00:00
00282a21a5
Use the personality function that was registered with MMI rather than
...
hardwiring in the C++ one.
llvm-svn: 36789
2007-05-05 20:27:00 +00:00
07e6f3257c
Propagate alignment/volatility in two places.
...
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1). This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll
llvm-svn: 36787
2007-05-05 19:39:05 +00:00
02528f5425
Spelling fix.
...
llvm-svn: 36781
2007-05-05 16:32:57 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
4cb9eb81ef
A bitcast of a global variable may have been constant folded to a GEP -
...
handle this case too.
llvm-svn: 36745
2007-05-04 17:12:26 +00:00
044a0a8cfb
Don't create indexed load / store with zero offset!
...
llvm-svn: 36716
2007-05-03 23:52:19 +00:00
44a2ed66b1
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
...
and PR1382
llvm-svn: 36672
2007-05-03 16:54:34 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
11940fbba3
Properly set arguments bitwidth of EHSELECT node
...
llvm-svn: 36654
2007-05-02 22:15:48 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
41223586a2
Fix build error.
...
llvm-svn: 36648
2007-05-02 20:37:47 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
8cd28f0fb1
If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames.
...
llvm-svn: 36625
2007-05-01 09:01:42 +00:00
b68343cdd8
Forgot about chain result; also UNDEF cannot have multiple values.
...
llvm-svn: 36622
2007-05-01 08:53:39 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
...
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
...
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
a684cd23a5
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
...
produce two results.)
* Do not touch volatile loads.
llvm-svn: 36604
2007-05-01 00:38:21 +00:00
4dbbace4ff
Fix PR1228 and CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
...
llvm-svn: 36602
2007-04-30 23:35:00 +00:00
f90c8fbd2b
print isLandingPad() for MBBs
...
llvm-svn: 36600
2007-04-30 23:12:53 +00:00
8cfd33b647
Continue refactoring inline asm code. If there is an earlyclobber output
...
register, preallocate all input registers and the early clobbered output.
This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
llvm-svn: 36599
2007-04-30 21:11:17 +00:00
6b77c3ed52
Updates.
...
llvm-svn: 36594
2007-04-30 18:42:09 +00:00
4333f8b1cf
refactor GetRegistersForValue to take OpInfo as an argument instead of various
...
pieces of it. No functionality change.
llvm-svn: 36592
2007-04-30 17:29:31 +00:00
ef07332504
refactor some code, no functionality change
...
llvm-svn: 36590
2007-04-30 17:16:27 +00:00
b58f93f273
Clean up multi-line asam string printing. Instead of printing:
...
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
print:
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
llvm-svn: 36589
2007-04-30 17:00:18 +00:00
412d61af43
generalize aggregate handling
...
llvm-svn: 36568
2007-04-29 18:58:03 +00:00
546ea7ea88
Implement review feedback
...
llvm-svn: 36564
2007-04-29 18:02:48 +00:00
401d8db381
memory operands that have a direct operand should have their stores created
...
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828
llvm-svn: 36547
2007-04-28 21:12:06 +00:00
de339fa55d
eliminate more redundant constraint type analysis
...
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
b2e55562ed
merge constraint type analysis stuff together.
...
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
d7e3b6c442
Significant refactoring of the inline asm stuff, to support future changes.
...
No functionality change.
llvm-svn: 36544
2007-04-28 20:49:53 +00:00
b18f8f85e9
Implement review feedback. Aliasees can be either GlobalValue's or
...
bitcasts of them.
llvm-svn: 36537
2007-04-28 13:45:00 +00:00
1deacd61f4
memory inputs to an inline asm are required to have an address available.
...
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
llvm-svn: 36536
2007-04-28 06:42:38 +00:00
d102ed0ac6
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
...
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
llvm-svn: 36534
2007-04-28 06:08:13 +00:00
4df3e8093b
Fix this to match change to InlineAsm class.
...
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
1cbe208cda
Fix incorrect legalization of EHSELECTOR. This fixes
...
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326
llvm-svn: 36510
2007-04-27 17:12:52 +00:00
bf535fc8bd
Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
...
llvm-svn: 36501
2007-04-27 07:33:31 +00:00
784fe9dbbb
improve EH global handling, patch by Duncan Sands.
...
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
8131ab7c0f
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
...
successfully! woohoo...
llvm-svn: 36496
2007-04-26 21:09:43 +00:00
d7ae7f1659
Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
...
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
e131e3ac02
Fix a typo in a comment.
...
llvm-svn: 36485
2007-04-26 19:40:56 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
ed23a1387e
Minor bug.
...
llvm-svn: 36473
2007-04-26 08:24:22 +00:00
43a17fe826
Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation.
...
llvm-svn: 36458
2007-04-26 01:40:09 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
d21968d11a
Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.
...
llvm-svn: 36451
2007-04-25 22:10:09 +00:00
d4549c5527
Clean up.
...
llvm-svn: 36449
2007-04-25 21:34:08 +00:00
0fbe14ab87
Data structure change to improve compile time (especially in debug mode).
...
llvm-svn: 36447
2007-04-25 19:34:00 +00:00
15f269afa3
This was lefted out. Fixed sumarray-dbl.
...
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
7818c03c6b
Fix for PR1306.
...
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.
llvm-svn: 36434
2007-04-25 07:30:23 +00:00
11dc5abde1
Clean up.
...
llvm-svn: 36431
2007-04-25 07:18:20 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
9bd98ea4c1
support > 4G stack objects
...
llvm-svn: 36422
2007-04-25 04:20:54 +00:00
cb0ed0cfbd
allow support for 64-bit stack objects
...
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
01a26c74ae
Be more careful about folding op(x, undef) when we have vector operands.
...
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll
llvm-svn: 36413
2007-04-25 00:00:45 +00:00
47917b697f
Assertion when using a 1-element vector for an add operation. Get the
...
real vector type in this case.
llvm-svn: 36402
2007-04-24 21:13:23 +00:00
4cfa616cee
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
...
tests always being true in the process.
llvm-svn: 36387
2007-04-24 01:24:20 +00:00
8653d29b45
modify per review commentary
...
llvm-svn: 36383
2007-04-23 23:33:31 +00:00
14a28f13c8
make EmitAlignment work the way Chris says it should
...
llvm-svn: 36368
2007-04-23 19:58:54 +00:00
8af6d5896f
PR400 phase 2. Propagate attributed load/store information through DAGs.
...
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
0c1349e6bc
Revert Christopher Lamb's load/store alignment changes.
...
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
bff50208c8
add support for alignment attributes on load/store instructions
...
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
94314be0e0
Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
...
llvm-svn: 36290
2007-04-20 23:02:39 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
4c53d321aa
VarInfo::UsedBlocks is no longer used. Remove.
...
llvm-svn: 36250
2007-04-18 05:04:38 +00:00
f03c90bee6
allow SRL to simplify its operands, as it doesn't demand all bits as input.
...
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
bf14f20632
When replacing a node in SimplifyDemandedBits, if the old node used any
...
single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
llvm-svn: 36244
2007-04-18 03:05:22 +00:00
15c1b820cc
fix a pasto
...
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
b408e8f11d
Don't populate TryAgainList when coalescing only physical registers with virtual registers.
...
llvm-svn: 36240
2007-04-18 02:30:19 +00:00
a5a0c7c909
Increment use count of new virtuals created during PHI elimination.
...
llvm-svn: 36233
2007-04-18 00:36:11 +00:00
4aff52bf3d
Fix a bug in my previous patch, grabbing the shift amount width from the
...
wrong operand.
llvm-svn: 36223
2007-04-17 22:53:02 +00:00
9a861a8550
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
...
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-17 21:14:16 +00:00
b881bdabd9
Copy coalescing change to prevent a physical register from being pin to a
...
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
first (if available) to create identify moves that can be eliminated.
llvm-svn: 36218
2007-04-17 20:32:26 +00:00
57b5214d59
Add a register allocation preference field; add a method to compute size of a live interval.
...
llvm-svn: 36216
2007-04-17 20:25:11 +00:00
8387cf1100
Keep track of number of uses within the function per virtual register.
...
llvm-svn: 36214
2007-04-17 20:22:11 +00:00
9ad5915559
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
...
a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
llvm-svn: 36212
2007-04-17 19:03:21 +00:00
58ec791b4c
Fix problems in the PartSet lowering having to do with incorrect bit width.
...
llvm-svn: 36180
2007-04-16 22:21:14 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
6bd7b7b30b
disable switch lowering using shift/and. It still breaks ppc bootstrap for
...
some reason. :( Will investigate.
llvm-svn: 36011
2007-04-14 19:39:41 +00:00
8a1a84f96e
Fix PR1325: Case range optimization was performed in the case it
...
shouldn't. Also fix some "latent" bug on 64-bit platforms
llvm-svn: 35990
2007-04-14 13:25:55 +00:00
7196f09edc
disable shift/and lowering to work around PR1325 for now.
...
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
e288040abf
Fix PR1323 : we haven't updated phi nodes in good manner :)
...
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
1b9213730f
Make sure intrinsics that are lowered to functions make the function weak
...
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.
llvm-svn: 35956
2007-04-12 21:53:38 +00:00
0f2f65f723
Fix bugs in generated code for part_select and part_set so that llc doesn't
...
barf when CBE is run with a program that contains these intrinsics.
llvm-svn: 35946
2007-04-12 13:30:14 +00:00
83faeb7611
Fix a bug in PartSet. The replacement value needs to be zext or trunc to
...
the size of the value, not just zext. Also, give better names to two BBs.
llvm-svn: 35945
2007-04-12 12:46:33 +00:00
5111499136
the result of an inline asm copy can be an arbitrary VT that the register
...
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
llvm-svn: 35944
2007-04-12 06:00:20 +00:00
a77cb3ce68
fold noop vbitconvert instructions
...
llvm-svn: 35943
2007-04-12 05:58:43 +00:00
784a68a702
Fix weirdness handling single element vectors.
...
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
c6251a7dfd
For PR1284:
...
Implement the "part_set" intrinsic.
llvm-svn: 35938
2007-04-12 02:48:46 +00:00
18e4ac4107
fix an infinite loop compiling ldecod, notice by JeffC.
...
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
a083ffcad7
Fix this harder.
...
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
c5f85d3738
don't create shifts by zero, fix some problems with my previous patch
...
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
65786b078c
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
...
allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
llvm-svn: 35883
2007-04-11 05:32:27 +00:00
41189c63cc
Codegen integer abs more efficiently using the trick from the PPC CWG. This
...
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old: X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecx addl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old: PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old: ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0 bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0 sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1: nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
llvm-svn: 35881
2007-04-11 05:11:38 +00:00
a472f66dd0
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
llvm-svn: 35877
2007-04-11 02:44:20 +00:00
f269d84ca0
apparently some people commit without building the tree, or they forget to
...
commit a LOT of files.
llvm-svn: 35858
2007-04-10 03:20:39 +00:00
e0bbbd3774
No longer needed.
...
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
35f0417ec1
remove dead target hooks.
...
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
da964a2852
Use integer log for metric calculation
...
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
0475f3b4e9
Unbreak VC++ build.
...
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
506eaf7915
Next stage into switch lowering refactoring
...
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
llvm-svn: 35816
2007-04-09 12:31:58 +00:00
71b79e3d99
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
7b2decfa0a
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
...
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
18d6718e78
add some assertions
...
llvm-svn: 35800
2007-04-09 05:23:13 +00:00
f73d215023
Fix a bug introduced with my previous patch, where it didn't correctly handle
...
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
llvm-svn: 35789
2007-04-09 01:19:33 +00:00
0df5357436
Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:
...
some instructions can have multiple frame indices in them. If this happens,
rewrite all of them.
llvm-svn: 35785
2007-04-09 00:46:10 +00:00
b49917da92
Fix PR1316
...
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
e55ecfb870
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
...
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
1c741e95d3
minor comment fix
...
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
85460acfbf
Change the bit_part_select (non)implementation from "return 0" to abort.
...
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
cce90f55ed
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
...
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
915e61736b
Properly emit range comparisons for switch cases, where neighbour cases
...
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
llvm-svn: 35672
2007-04-04 21:14:49 +00:00
8be98c1572
Re-materialize all loads from fixed stack slots.
...
llvm-svn: 35660
2007-04-04 07:40:01 +00:00
2bf2aadd9a
Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.
...
llvm-svn: 35658
2007-04-04 07:04:55 +00:00
06a7041ff9
Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.
...
llvm-svn: 35618
2007-04-03 06:43:29 +00:00
16627a542f
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
...
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
llvm-svn: 35605
2007-04-02 21:36:32 +00:00
476fb6a5c9
Ugh. Copy coalescer does not update register numbers.
...
llvm-svn: 35600
2007-04-02 18:49:18 +00:00
fad9bd6b92
For PR1297:
...
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).
llvm-svn: 35567
2007-04-02 01:01:49 +00:00
6bba6c8143
For PR1297:
...
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.
llvm-svn: 35547
2007-04-01 07:35:23 +00:00
3a0843e734
For PR1297:
...
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
llvm-svn: 35546
2007-04-01 07:34:11 +00:00
a090ffb2ab
For PR1297:
...
Change getOperationName to return std::string instead of const char*
llvm-svn: 35545
2007-04-01 07:32:19 +00:00
f6a6d3c8b0
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
...
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
f2d71d49e2
switch TL::getValueType to use MVT::getValueType.
...
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
bafc837c83
Add a -print-lsr-output option to LLC, to print the output of the LSR pass.
...
llvm-svn: 35522
2007-03-31 00:24:43 +00:00
ac3f81508c
add one addressing mode description hook to rule them all.
...
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
4bbd2eefba
Fix incorrect combination of different loads. Reenable zext-over-truncate
...
combination.
llvm-svn: 35517
2007-03-30 21:38:07 +00:00
9a2a7b174a
Don't add the same MI to register reuse "last def/use" twice if it reads the
...
register more than once.
llvm-svn: 35513
2007-03-30 20:21:35 +00:00
48dd5e7d44
Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length
...
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.
llvm-svn: 35512
2007-03-30 20:18:35 +00:00
ccee35fd0d
Disable load width reduction xform of variant (zext (truncate load x)) for
...
big endian targets until llvm-gcc build issue has been resolved.
llvm-svn: 35449
2007-03-29 07:56:46 +00:00
86de3a009d
New entries.
...
llvm-svn: 35445
2007-03-29 02:48:56 +00:00
d771485d89
Notes on re-materialization.
...
llvm-svn: 35420
2007-03-28 08:30:04 +00:00
603e49c6da
Move rematerialization out of beta.
...
llvm-svn: 35419
2007-03-28 08:26:40 +00:00
4388043b25
Scale 1 is always ok.
...
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
07c42d43a2
GEP index sinking fixes:
...
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
llvm-svn: 35403
2007-03-28 01:49:39 +00:00
b41697c006
Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should
...
not violate that.
llvm-svn: 35396
2007-03-28 01:30:37 +00:00
37a0bfe128
Remove dead code
...
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
3a9d68181a
Split big monster into small helpers. No functionality change.
...
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
c42406b5ad
SDISel does not preserve all, it changes CFG and other info.
...
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
fdbdf43632
Don't call getOperandConstraint() if operand index is greater than
...
TID->numOperands.
llvm-svn: 35375
2007-03-27 00:48:28 +00:00
4a09b1b5be
Fix for PR1266. Don't mark a two address operand IsKill.
...
llvm-svn: 35365
2007-03-26 22:40:42 +00:00
ec3ac316e2
Change findRegisterUseOperand() to return operand index instead.
...
llvm-svn: 35363
2007-03-26 22:37:45 +00:00
fd18a0cdf4
Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
...
hopefully forestall similar errors.
llvm-svn: 35362
2007-03-26 22:23:54 +00:00
8275f0e0af
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
...
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
7037826c86
First step of switch lowering refactoring: perform worklist-driven
...
strategy, emit JT's where possible.
llvm-svn: 35338
2007-03-25 15:07:15 +00:00
77f0479833
Implement support for vector operands to inline asm, implementing
...
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
llvm-svn: 35332
2007-03-25 05:00:54 +00:00
3d7efa2586
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
...
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
843e44503c
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
...
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
2a991268f7
don't rely on ADL
...
llvm-svn: 35299
2007-03-24 17:37:03 +00:00
b7051f596a
Adjust offset to compensate for big endian machines.
...
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
a883b58caf
Make sure SEXTLOAD of the specific type is supported on the target.
...
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
e2f5f24e8e
Also replace uses of SRL if that's also folded during ReduceLoadWidth().
...
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
a824e79f06
A couple of bug fixes for reducing load width xform:
...
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.
llvm-svn: 35274
2007-03-23 02:16:52 +00:00
dcb291faa4
Change uses of Function::front to Function::getEntryBlock for readability.
...
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
464dc9b74c
More opportunities to reduce load size.
...
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
a20815e157
Fix for PR1257. Bug in live range shortening as a result of copy coalescing
...
where the destination is dead.
llvm-svn: 35252
2007-03-22 01:26:05 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
d63baead9b
fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
...
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
3578dd61c6
Potential spiller improvement.
...
llvm-svn: 35228
2007-03-20 22:22:38 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
d05a1a2ade
maintain LiveIn when splitting blocks (register scavenging needs it)
...
llvm-svn: 35226
2007-03-20 21:35:06 +00:00
1baf5c84ab
Fix some VC++ warnings.
...
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
971aa18867
Code clean up.
...
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
550cf0369c
Minor bug.
...
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
25878b45f5
CopyToReg source operand can be a physical register.
...
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
0e3278e505
First cut trivial re-materialization support.
...
llvm-svn: 35208
2007-03-20 08:13:50 +00:00
25d00d545d
Remove -reduce-joining-phys-regs options. Make it on by default.
...
llvm-svn: 35165
2007-03-19 18:08:26 +00:00
c5e74f6404
Minor bug fix.
...
llvm-svn: 35153
2007-03-19 04:22:35 +00:00
d8f2e4fe4c
- Merge UsedBlocks info after two virtual registers are coalesced.
...
- Use distance to closest use to determine whether to abort coalescing.
llvm-svn: 35141
2007-03-18 09:05:55 +00:00
5382426577
Keep UsedBlocks info accurate.
...
llvm-svn: 35140
2007-03-18 09:02:31 +00:00
f6f043332f
Track the BB's where each virtual register is used.
...
llvm-svn: 35135
2007-03-17 09:29:54 +00:00
7b2a001669
Joining a live interval of a physical register with a virtual one can turn out
...
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!
Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.
llvm-svn: 35134
2007-03-17 09:27:35 +00:00
a2465dfc07
Use SmallSet instead of std::set.
...
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
be22235790
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
...
in that BB.
llvm-svn: 35132
2007-03-17 08:22:49 +00:00
c5bc763f50
Turn on GEP index sinking by default.
...
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
0a9d0cabaf
Stupid bug.
...
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
009ea54262
Sink a binary expression into its use blocks if it is a loop invariant
...
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
llvm-svn: 35123
2007-03-16 08:46:27 +00:00
a2a2fd1e55
Added isLegalAddressExpression hook to test if the given expression can be
...
folded into target addressing mode for the given type.
llvm-svn: 35121
2007-03-16 08:42:32 +00:00
88de94a4fb
Debugging output stuff.
...
llvm-svn: 35117
2007-03-15 21:19:28 +00:00
b9e3db67fb
Estimate a cost using the possible number of scratch registers required and use
...
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
2874855302
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
...
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
b7004fd889
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
df7949a8d0
If a virtual register is already marked alive in this block, that means it is
...
alive in one of the successor block. Do not add it to the kill list.
llvm-svn: 35041
2007-03-09 09:48:56 +00:00
9bc8d4b6f2
Print preds / succs BB numbers.
...
llvm-svn: 35040
2007-03-09 08:29:08 +00:00
91b0790297
Avoid variable shadowing.
...
llvm-svn: 35039
2007-03-09 06:02:17 +00:00
ce8aba03ee
implement support for floating point constants used as inline asm memory operands.
...
llvm-svn: 35033
2007-03-08 22:29:47 +00:00
b7bc3f2d30
make this fail even in non-assert builds.
...
llvm-svn: 35025
2007-03-08 07:07:03 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
dd6ce6900e
Cleanup: make SetCounter an instance variable
...
llvm-svn: 35007
2007-03-07 08:25:02 +00:00
8a1d09d079
Avoid combining indexed load further.
...
llvm-svn: 35005
2007-03-07 08:07:03 +00:00
942fda027f
Fix DWARF debugging information on x86/Linux and (hopefully)
...
Mingw32/Cygwin targets. This fixes PR978
llvm-svn: 35000
2007-03-07 02:47:57 +00:00
24f65cc91e
Minor bug fix.
...
llvm-svn: 34985
2007-03-06 21:58:15 +00:00
b0743b5d6a
Now LoopStrengthReduce is a LoopPass.
...
llvm-svn: 34984
2007-03-06 21:14:09 +00:00
13780ac7db
big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
...
the lo-reg first. This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx
llvm-svn: 34983
2007-03-06 20:01:06 +00:00
6c5e0ad71c
Small eye-candy: use asciz directive everywhere, where possible.
...
llvm-svn: 34981
2007-03-06 19:25:02 +00:00
c1b21857a4
If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer.
...
llvm-svn: 34965
2007-03-06 10:02:38 +00:00
372c2c69f8
Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available.
...
llvm-svn: 34964
2007-03-06 10:01:25 +00:00
f0b9316552
Enumerate SDISel formal parameter attributes. Make use of new
...
enumeration.
llvm-svn: 34960
2007-03-06 06:10:33 +00:00
b622c11f77
Unbreak VC++ build.
...
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
47206667c0
fold away addc nodes when we know there cannot be a carry-out.
...
llvm-svn: 34913
2007-03-04 20:40:38 +00:00
2dcc6e7f58
generalize
...
llvm-svn: 34910
2007-03-04 20:08:45 +00:00
e2e13caeb2
canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of
...
addc, turn it into add.
This allows us to compile:
long long test(long long A, unsigned B) {
return (A + ((long long)B << 32)) & 123;
}
into:
_test:
movl $123, %eax
andl 4(%esp), %eax
xorl %edx, %edx
ret
instead of:
_test:
xorl %edx, %edx
movl %edx, %eax
addl 4(%esp), %eax ;; add of zero
andl $123, %eax
ret
llvm-svn: 34909
2007-03-04 20:03:15 +00:00
362621c7ae
eliminate some ops if they have an undef RHS
...
llvm-svn: 34908
2007-03-04 20:01:46 +00:00
b8825b8c04
Remove unneeded header file.
...
llvm-svn: 34903
2007-03-04 04:41:04 +00:00
ca401aac31
Fix CodeGen/Generic/fpowi-promote.ll and PR1239
...
llvm-svn: 34893
2007-03-03 23:43:21 +00:00
567b9254cd
Add an expand action for ISD label which just deletes the label.
...
This "fixes" PR1238.
llvm-svn: 34890
2007-03-03 19:21:38 +00:00
d74cb0e194
Only propagate IsKill if the last use is a kill.
...
llvm-svn: 34878
2007-03-03 06:32:37 +00:00
323cf8f602
http://llvm.org/bugs/show_bug.cgi?id=1237
...
llvm-svn: 34875
2007-03-03 06:18:18 +00:00
3fd728596e
Watch out for cases like this:
...
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
%reg1032 = tMOVrr %r3<kill>
%reg1033 = tMOVri8 1
%reg1034 = tMOVri8 0
tCMPi8 %reg1029<kill>, 0
tBcc mbb<entry,0x8b06a10>, 0
Successors according to CFG: 0x8b06980 0x8b06a10
entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
Predecessors according to CFG: 0x8b056f0
%reg1036 = tMOVrr %reg1034<kill>
Successors according to CFG: 0x8b06a10
entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
Predecessors according to CFG: 0x8b056f0 0x8b06980
%reg1024<dead> = tMOVrr %reg1030<kill>
...
reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.
llvm-svn: 34866
2007-03-03 02:18:00 +00:00
155ede21e0
Mark dead def as unused.
...
llvm-svn: 34844
2007-03-02 10:43:16 +00:00
9d615d1e70
Dead live-in detection bug.
...
llvm-svn: 34843
2007-03-02 10:41:15 +00:00
6605c5dbee
- Keep track all def and uses of stack slot available in register.
...
- Available value use may be deleted (e.g. noop move).
llvm-svn: 34841
2007-03-02 08:52:00 +00:00
08f2f0d145
Invalidate last use of a reused register if the use is a deleted noop copy.
...
llvm-svn: 34839
2007-03-02 05:41:42 +00:00
82af5943d1
Emit eh filter info.
...
llvm-svn: 34805
2007-03-01 20:26:43 +00:00
6458e6acb9
Collect eh filter info.
...
llvm-svn: 34804
2007-03-01 20:25:32 +00:00
d5453d7b56
Lower eh filter intrinsic.
...
llvm-svn: 34802
2007-03-01 20:24:30 +00:00
105fb1e0dd
Delete register scavenger when done with it.
...
llvm-svn: 34786
2007-03-01 10:23:33 +00:00
27bc565497
Add a version of FindUnusedReg that restrict search to a specific set of registers.
...
llvm-svn: 34784
2007-03-01 08:56:24 +00:00
d6450ba1dc
A restore is promoted to copy (or deleted entirely), remove the kill from the last use of the targetted register.
...
llvm-svn: 34773
2007-03-01 02:27:30 +00:00
31215d1395
Interface clean up.
...
llvm-svn: 34772
2007-03-01 02:25:51 +00:00
428eaa0059
Interface clean up.
...
llvm-svn: 34770
2007-03-01 02:19:39 +00:00
9be123c568
Oops.
...
llvm-svn: 34768
2007-03-01 02:05:35 +00:00
8a703ad4b6
Track all joined registers and eliminate unneeded kills after all joining are done.
...
llvm-svn: 34767
2007-03-01 02:03:03 +00:00
644af6b68f
Chain is on second operand.
...
llvm-svn: 34759
2007-02-28 20:43:58 +00:00
c46bf3577d
Handle mix of personalities.
...
llvm-svn: 34752
2007-02-28 18:38:31 +00:00
c114990526
Provide a more meaningful name.
...
llvm-svn: 34751
2007-02-28 18:37:50 +00:00
cf465fcebc
MERGE_VALUES unnecessary.
...
llvm-svn: 34750
2007-02-28 18:37:04 +00:00
37dc4b5bb3
Fix a typo, thanks Bill!
...
llvm-svn: 34741
2007-02-28 09:16:38 +00:00
e0232ec706
More Mach-O writer improvements.
...
llvm-svn: 34740
2007-02-28 07:40:50 +00:00
74bb92902e
add methods for analysis of call results and return nodes.
...
llvm-svn: 34738
2007-02-28 07:09:40 +00:00
e74744143f
add methods to analyze calls and formals.
...
llvm-svn: 34736
2007-02-28 06:56:37 +00:00
b5582bf984
add a newline at end of file
...
llvm-svn: 34735
2007-02-28 06:42:11 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
...
llvm-svn: 34711
2007-02-28 00:59:19 +00:00
589ba3964b
MRegisterInfo disowns RegScavenger. It's immutable.
...
llvm-svn: 34706
2007-02-28 00:17:36 +00:00
a7e4b60b85
Some more code clean up.
...
llvm-svn: 34700
2007-02-27 22:58:43 +00:00
8a8dc04e7e
Oops.
...
llvm-svn: 34698
2007-02-27 22:10:52 +00:00
e50a994cba
Let MRegisterInfo now owns RegScavenger.
...
llvm-svn: 34691
2007-02-27 21:10:33 +00:00
51f54640de
RegScavenger interface change to make it more flexible.
...
llvm-svn: 34690
2007-02-27 21:09:48 +00:00
9f059194a7
Minor refactoring of CC Lowering interfaces
...
llvm-svn: 34656
2007-02-27 05:13:54 +00:00
dc3adc83e7
move CC Lowering stuff to its own public interface
...
llvm-svn: 34655
2007-02-27 04:43:02 +00:00
ca25c0ee0d
forward() should not increment internal iterator. Its client may insert instruction between now and next forward() call.
...
llvm-svn: 34649
2007-02-27 01:58:48 +00:00
bdec83e4d2
Joining an interval with a dead copy instruction. Shorten the live range to the last use.
...
llvm-svn: 34645
2007-02-26 21:37:37 +00:00
fce448f856
Fold (sext (truncate x)) more aggressively, by avoiding creation of a
...
sextinreg if not needed. This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed. After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.
llvm-svn: 34621
2007-02-26 03:13:59 +00:00
ab5d0ac02c
track signedness of formal argument, though we have a fixme here.
...
llvm-svn: 34620
2007-02-26 02:56:58 +00:00
14059d958a
Fix for PR1224.
...
llvm-svn: 34610
2007-02-25 21:43:59 +00:00
8c504cf9a0
optimize duplicate ValueMap lookups
...
llvm-svn: 34599
2007-02-25 18:40:32 +00:00
38fd9b074f
A couple of more places where a register liveness has been extended and its last kill should be updated accordingly.
...
llvm-svn: 34597
2007-02-25 09:51:27 +00:00
fb2333a333
Add an assertion.
...
llvm-svn: 34596
2007-02-25 09:47:31 +00:00
0577b51538
Fix a couple of bugs related IsDead back propagation during coalescing.
...
llvm-svn: 34595
2007-02-25 09:46:31 +00:00
e54eb80720
If the liveinterval of the source instruction has been extended, remove the IsKill marker.
...
llvm-svn: 34594
2007-02-25 09:41:59 +00:00
220a7af107
Only add liveinterval to livein set if it isn't assigned a stack slot.
...
llvm-svn: 34593
2007-02-25 09:39:02 +00:00
387f464121
fold trivial token factor nodes. This allows us to compile
...
test/CodeGen/X86/fp-stack-ret.ll into:
movl 4(%esp), %eax
fldl (%eax)
ret
instead of:
subl $12, %esp
movl 16(%esp), %eax
movsd (%eax), %xmm0
movsd %xmm0, (%esp)
fldl (%esp)
addl $12, %esp
ret
by eliminating a token factor that blocked a check.
llvm-svn: 34584
2007-02-25 08:24:27 +00:00
168c5856bf
initialize a instance variable
...
llvm-svn: 34567
2007-02-25 01:28:05 +00:00
e1d1c0590f
Deal with cases when MMI is not requested.
...
llvm-svn: 34556
2007-02-24 09:45:44 +00:00
b869ab6f31
Drop unused operand.
...
llvm-svn: 34555
2007-02-24 09:44:17 +00:00
d7ef3f804d
Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219
...
llvm-svn: 34551
2007-02-24 02:09:29 +00:00
520b20d3b7
Reuse extends the liveness of a register. Transfer the kill to the operand that reuse it.
...
llvm-svn: 34536
2007-02-23 21:47:50 +00:00
31fef788eb
Handle improper cast.
...
llvm-svn: 34535
2007-02-23 21:45:01 +00:00
97cc93841d
Handle cases when joining live intervals of two virtual registers.
...
llvm-svn: 34534
2007-02-23 20:40:13 +00:00
584e051c28
Mark livein registers as being in used.
...
llvm-svn: 34525
2007-02-23 08:41:19 +00:00
f7e320c9e0
A spill kills the register being stored. But it is later being reused by spiller, its live range has to be extended.
...
llvm-svn: 34517
2007-02-23 01:13:26 +00:00
1e56453585
First potential client of register scavenger.
...
llvm-svn: 34516
2007-02-23 01:11:26 +00:00
9965aebd5d
Use findRegisterUseOperand to find a kill of particular register.
...
llvm-svn: 34512
2007-02-23 01:04:26 +00:00
956fdeb694
Initial check in of register scavenger. Its only current functionality is tracking live registers per MBB.
...
llvm-svn: 34511
2007-02-23 01:01:19 +00:00
cc607daac1
Remove unnecessary isKill properties if a live range has been lengthened due to coalescing.
...
llvm-svn: 34503
2007-02-22 23:03:39 +00:00
5cbb4262ab
Update comment.
...
llvm-svn: 34502
2007-02-22 18:51:19 +00:00
66aa84d12f
Missing end of abbreviations - correction
...
llvm-svn: 34501
2007-02-22 18:48:52 +00:00
4e3d2b9acc
Missing end of abbreviations.
...
llvm-svn: 34500
2007-02-22 18:22:42 +00:00
3e3a65b764
Need to init.
...
llvm-svn: 34499
2007-02-22 18:04:49 +00:00
9df1a1d8d8
Remove isAccessable.
...
llvm-svn: 34497
2007-02-22 16:39:03 +00:00
69bd45c1d2
Use exception flag.
...
llvm-svn: 34496
2007-02-22 16:22:15 +00:00
46dbe12b32
Remove assertion.
...
llvm-svn: 34494
2007-02-22 16:12:17 +00:00
44c37e7dbf
Tighten up error checking of args.
...
llvm-svn: 34493
2007-02-22 16:10:05 +00:00
504e99479c
Handle lowering invoke to call correctly.
...
llvm-svn: 34492
2007-02-22 15:38:06 +00:00
7f5872c455
Simplify lowering and selection of exception ops.
...
llvm-svn: 34491
2007-02-22 15:37:19 +00:00
4b37a4c712
Selection and lowering for exception handling.
...
llvm-svn: 34481
2007-02-21 22:53:45 +00:00
09953e6482
Exception handling support.
...
llvm-svn: 34479
2007-02-21 22:48:45 +00:00
18fc09723c
Add support for changes in DwarfWriter.
...
llvm-svn: 34478
2007-02-21 22:47:38 +00:00
2dc5245c4a
Make branch folding behave in the presence of landing pads.
...
llvm-svn: 34476
2007-02-21 22:42:20 +00:00
5b2b7c1024
Allow for live in registers for eh landing pads.
...
llvm-svn: 34475
2007-02-21 22:41:17 +00:00
88dd2fd332
Add structures used for collecting eh information.
...
llvm-svn: 34473
2007-02-21 22:38:31 +00:00
e563c7eb27
Out of bound reference.
...
llvm-svn: 34461
2007-02-21 02:27:39 +00:00
de037a821a
Use BitVector instead. No functionality change.
...
llvm-svn: 34460
2007-02-21 02:22:03 +00:00
61cd0914ed
Dead code.
...
llvm-svn: 34435
2007-02-20 01:29:10 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
2605082f0e
- Changes how function livein's are handled, they now have a start index of 0.
...
- When coalescing a copy MI, if its destination is "dead", propagate the
property to the source MI's destination if there are no intervening uses.
- Detect dead function live-in's and remove them.
llvm-svn: 34383
2007-02-17 11:15:40 +00:00
a3d3599210
Do not add livein's to entry MBB twice.
...
llvm-svn: 34382
2007-02-17 11:11:27 +00:00
41d2a1d8bf
Added removeLiveIn.
...
llvm-svn: 34381
2007-02-17 11:10:48 +00:00
6accd480a2
Added findRegisterDefOperand().
...
llvm-svn: 34380
2007-02-17 11:10:18 +00:00
ef932b067d
- Use MRegister::regsOverlap().
...
- Allow LiveVariables to track liveness of more registers.
llvm-svn: 34379
2007-02-17 11:09:47 +00:00
56e5fea163
print target nodes nicely
...
llvm-svn: 34369
2007-02-17 06:38:37 +00:00
a9f917af59
Implement i/n/s constraints correctly. This fixes
...
test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
llvm-svn: 34368
2007-02-17 06:00:35 +00:00
12920dda9e
Fixes PR 1200
...
llvm-svn: 34359
2007-02-17 00:44:34 +00:00
66cb162f92
Print <dead> def operands.
...
llvm-svn: 34343
2007-02-16 09:49:18 +00:00
7238410766
Add live-ins to every BB.
...
llvm-svn: 34342
2007-02-16 09:05:02 +00:00
915e15481e
test commit (blank line)
...
llvm-svn: 34337
2007-02-16 01:54:53 +00:00
68dcec6fea
fix indentation
...
llvm-svn: 34307
2007-02-15 18:19:15 +00:00
21ebae3394
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
...
abort case.
llvm-svn: 34306
2007-02-15 18:17:56 +00:00
14edd1989b
Use BitVector instead of vector<bool> which can be extremely slow.
...
llvm-svn: 34302
2007-02-15 05:59:24 +00:00
09575bac2e
For PR1195:
...
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
llvm-svn: 34300
2007-02-15 03:39:18 +00:00
d84d35ba70
For PR1195:
...
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.
llvm-svn: 34293
2007-02-15 02:26:10 +00:00
ab1812f806
fix a warning
...
llvm-svn: 34272
2007-02-14 07:34:56 +00:00
1cf84d2745
Refix CodeGen/Generic/switch-lower.ll. In contrast to my previous patch,
...
this doesn't miscompile lots of programs :)
llvm-svn: 34268
2007-02-14 07:18:16 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
59b27fa371
implement expand of truncate. This allows truncates from i128 to i64 to
...
be supported on 32-bit hosts.
llvm-svn: 34257
2007-02-13 23:55:16 +00:00
d08d31f68a
Fix PR1198, by adding initial i128 support. Patch by Dan Gohman.
...
llvm-svn: 34256
2007-02-13 23:41:38 +00:00
2fbff4d2dc
revert my previous switch lowering change, which miscompiles a few programs.
...
This will break a dj test until I have time to investigate.
llvm-svn: 34247
2007-02-13 20:09:07 +00:00
abde3cc16c
Add a space between // and the comment.
...
llvm-svn: 34244
2007-02-13 18:10:13 +00:00
9956dcffbe
Add "original alignment" to function arguments flags.
...
llvm-svn: 34240
2007-02-13 13:50:08 +00:00
6ea07f178c
eliminate vector-related allocations
...
llvm-svn: 34223
2007-02-13 06:01:22 +00:00
b612316f20
Allow any MachineBasicBlock (not just the entry block) to have live-in physical
...
registers. Make sure liveinterval analysis is correctly creating live ranges
for them.
llvm-svn: 34217
2007-02-13 01:30:55 +00:00
9056bae3be
Fix switch lowering to order cases in zext order, which is how we emit the
...
comparisons. This fixes an infinite loop on CodeGen/Generic/switch-lower.ll
and PR1197
llvm-svn: 34216
2007-02-13 01:05:56 +00:00
83dfca816c
eliminate temporary vectors.
...
llvm-svn: 34161
2007-02-10 20:31:59 +00:00
b84892d2d2
encapsulate the rest of the StructLayout members.
...
llvm-svn: 34157
2007-02-10 19:59:22 +00:00
c473d8e431
Privatize StructLayout::MemberOffsets, adding an accessor
...
llvm-svn: 34156
2007-02-10 19:55:17 +00:00
276b44b0f9
Add function live-ins to entry block live-in set.
...
llvm-svn: 34112
2007-02-10 02:43:39 +00:00
bcf1d7faef
Add live-ins to MachineBasicBlock.
...
llvm-svn: 34111
2007-02-10 02:38:19 +00:00
de6083463d
Rename some variables to avoid confusion with SelectionDAGISel::BB.
...
llvm-svn: 34110
2007-02-10 01:08:18 +00:00
93049457ee
Make use of TLI.SimplifySetCC() in LegalizeSetCCOperands().
...
llvm-svn: 34066
2007-02-08 22:16:19 +00:00
92658d5648
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
...
llvm-svn: 34065
2007-02-08 22:13:59 +00:00
6ad6fdb70b
Fixed a long standing spiller bug that's exposed by Thumb:
...
The code sequence before the spiller is something like:
= tMOVrr
%reg1117 = tMOVrr
%reg1078 = tLSLri %reg1117, 2
The it starts spilling:
%r0 = tRestore <fi#5>, 0
%r1 = tRestore <fi#7>, 0
%r1 = tMOVrr %r1<kill>
tSpill %r1, <fi#5>, 0
%reg1078 = tLSLri %reg1117, 2
It restores the value while processing the first tMOVrr. At this point, the
spiller remembers fi#5 is available in %r0. Next it processes the second move.
It restores the source before the move and spills the result afterwards. The
move becomes a noop and is deleted. However, a spill has been inserted and that
should invalidate reuse of %r0 for fi#5 and add reuse of %r1 for fi#5.
Therefore, %reg1117 (which is also assigned fi#5) should get %r1, not %r0.
llvm-svn: 34039
2007-02-08 06:04:54 +00:00
523048ecde
Split the addPassesToEmitFile method up into two. This is so that we can
...
do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.
llvm-svn: 34032
2007-02-08 01:36:53 +00:00
3c4d37a531
Add function to create a file writer.
...
llvm-svn: 34031
2007-02-08 01:35:27 +00:00
860ce1b82e
Moved from include/llvm/CodeGen to lib/CodeGen.
...
llvm-svn: 34027
2007-02-08 01:30:50 +00:00
3cc886add8
Fix a fixme by correctly calculating preferred alignments for functions,
...
based on the alignment of the symbol and the target data's preferred align
for that type.
Also, rename some arguments for consistency.
llvm-svn: 33984
2007-02-07 05:47:16 +00:00
dc0a9a7b4a
Two fixes:
...
1. Memset takes an i32 for the value to set, not i8. This was causing GCC to
ICE all over the place (PR1183).
2. memcpy/memmove were not properly zext/trunc'ing the size in some cases.
llvm-svn: 33970
2007-02-06 19:06:38 +00:00
1b4b054cba
Fix PR1181 and CodeGen/CBackend/2007-02-05-memset.ll
...
llvm-svn: 33957
2007-02-06 06:07:51 +00:00
89e66e0c26
Oops, swap this. This fixes a regression I introduced in the ARM backend.
...
llvm-svn: 33946
2007-02-06 01:56:31 +00:00
a9428c4f9d
Fix PR1178
...
llvm-svn: 33924
2007-02-05 21:23:52 +00:00
465c0253c3
Fixing silly "not-implemented" bug in AsmPrinter. This fixes PR1169.
...
llvm-svn: 33888
2007-02-04 23:27:42 +00:00
19083a4671
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
...
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
llvm-svn: 33879
2007-02-04 08:47:20 +00:00
9af2c86bc8
Introduce new UnarySDNode/BinarySDNode/TernarySDNode nodes, which coallocate
...
their operands with the node itself. This reduces malloc traffic for operand
lists. This reduces isel time on kc++ from 2.6164 to 2.5570s, about 2.3%.
llvm-svn: 33878
2007-02-04 08:35:21 +00:00
22639f3d90
eliminate the SDNode::setValueTypes method.
...
llvm-svn: 33876
2007-02-04 07:37:24 +00:00
f17b4222e2
eliminate a bunch of duplicate ctors and helper functions.
...
llvm-svn: 33875
2007-02-04 07:28:00 +00:00
edfc7e5fa2
move MorphNode to out of line and merge setNodeOperands into it. There is
...
no behavior or performance change here.
llvm-svn: 33869
2007-02-04 02:49:29 +00:00
3bf17b6fa5
simplify MorphNodeTo to take a VTList operand.
...
llvm-svn: 33868
2007-02-04 02:41:42 +00:00
486edfbc6f
eliminate some extraneous methods in SDNode
...
llvm-svn: 33867
2007-02-04 02:32:44 +00:00
20754cc579
Give each selectiondag node class a home for it's vtable and rtti info
...
llvm-svn: 33866
2007-02-04 02:23:32 +00:00
289aa4495c
Switch VAlueMap from std::map to DenseMap.
...
llvm-svn: 33863
2007-02-04 01:35:11 +00:00
79084305ee
Switch NodeMap from std::map to DenseMap, this speeds up isel by 2.3%
...
llvm-svn: 33862
2007-02-04 01:31:47 +00:00
94c44c96d3
swtich vector-> smallvector, speeding up selectiondag stuff 1%
...
llvm-svn: 33861
2007-02-04 01:20:02 +00:00
4b0ddb22e9
Switch promoted/expanded ops over to using a DenseMap. Vector related maps
...
aren't worth it.
llvm-svn: 33860
2007-02-04 01:17:38 +00:00
ed39c86176
switch LegalizedNodes from std::map to a DenseMap. This speeds up isel
...
time as a whole on kc++ by 11%.
llvm-svn: 33857
2007-02-04 00:50:02 +00:00
ebeb48d4bc
Eliminate some malloc traffic from LegalizeAllNodesNotLeadingTo, speeding
...
up isel on kimwitu by 0.7%.
llvm-svn: 33853
2007-02-04 00:27:56 +00:00
cba058ce51
Eliminate some std::sets. This speeds up isel of kimwitu by about 0.9%
...
llvm-svn: 33852
2007-02-04 00:24:41 +00:00
feec7137ce
Switch SelectionDAG::ReplaceAllUsesOfValueWith to use a SmallSetVector for
...
the users set (most nodes have 1 or 2 users). This speeds up the isel pass
3.2% on kimwitu.
llvm-svn: 33849
2007-02-04 00:14:31 +00:00
c27c70dc3d
Pass in non-Mach-O-specific parameters to the GetTargetRelocation method.
...
llvm-svn: 33816
2007-02-03 02:39:40 +00:00
0a30b1f00f
switch the sched unit map over to use a DenseMap instead of std::map. This
...
speeds up isel as a whole time by 2.6%.
llvm-svn: 33810
2007-02-03 01:34:13 +00:00
e83030b9c8
Switch ComputeTopDownOrdering over to using a densemap. This speeds up
...
isel as a whole by 3.3%.
llvm-svn: 33809
2007-02-03 01:12:36 +00:00
f309d13677
Pasto
...
llvm-svn: 33806
2007-02-03 00:43:46 +00:00
5dc84cdab7
Use short form of BinaryOperator create function.
...
llvm-svn: 33784
2007-02-02 14:09:34 +00:00
2341c22ec7
Changes to support making the shift instructions be true BinaryOperators.
...
This feature is needed in order to support shifts of more than 255 bits
on large integer types. This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
shl i32 %X, 1
instead of
shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.
llvm-svn: 33776
2007-02-02 02:16:23 +00:00
f970221c4d
Slip up
...
llvm-svn: 33758
2007-02-01 17:48:20 +00:00
894ceb1c6f
Emit labels as label_n and not as debug_n
...
llvm-svn: 33757
2007-02-01 17:46:10 +00:00
c3de9b4b14
Support for non-landing pad exception handling.
...
llvm-svn: 33755
2007-02-01 16:31:34 +00:00
1b4e6015b4
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
...
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144
llvm-svn: 33752
2007-02-01 08:39:52 +00:00
1003dc72b4
rename DenseMap to IndexedMap.
...
llvm-svn: 33749
2007-02-01 05:32:05 +00:00
296a83cefb
Fit in 80 columns
...
llvm-svn: 33745
2007-02-01 04:55:59 +00:00
e3eeb24a86
Emit a better assertion message for PR1133
...
llvm-svn: 33736
2007-02-01 01:21:12 +00:00
53026f1d5a
Allow the target to override the ISD::CondCode that's to be used to test the
...
result of the comparison libcall against zero.
llvm-svn: 33701
2007-01-31 09:29:11 +00:00
5301e7c605
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
...
confusion with external linkage types.
llvm-svn: 33663
2007-01-30 20:08:39 +00:00
d27f95e08d
add initial support for handling inline asms with multiple constraints.
...
This doesn't do the "right thing" but will probably work in most cases.
This implements CodeGen/PowerPC/2007-01-29-lbrx-asm.ll.
llvm-svn: 33643
2007-01-29 23:45:14 +00:00
ee23de6c36
Out of line function.
...
llvm-svn: 33641
2007-01-29 23:40:33 +00:00
3f9f250928
Only gather frame info if debug or eh.
...
llvm-svn: 33639
2007-01-29 23:20:22 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
2a562ba47b
Properly support cstrings
...
llvm-svn: 33629
2007-01-29 21:20:42 +00:00
d1154860a4
Flag to control exception handling.
...
llvm-svn: 33628
2007-01-29 20:48:32 +00:00
18c3b5267d
Disable zero landing pads for now.
...
llvm-svn: 33625
2007-01-29 20:01:41 +00:00
b4a2f05d1c
Landing pad-less eh for PPC.
...
llvm-svn: 33622
2007-01-29 18:51:14 +00:00
d7035b654b
Use TargetData to obtain the correct size of the "size_t" argument for
...
functions like memcpy, memmove and memset. Ensure only one prototype is
used for these functions and that it matches the system definition by
using the appropriate type for the size argument.
llvm-svn: 33618
2007-01-29 17:42:06 +00:00
c7765617d2
For PR1138:
...
Force memcpy to be the 32-bit variant. Since this is only used with
CBE and lli which both target 32-bit machines, this should be okay.
llvm-svn: 33608
2007-01-28 22:28:00 +00:00
06f7d4bec7
Arguments are counting from 1. not from 0. Maybe we should change
...
numbering somehow? E.g. make return argument the last?
llvm-svn: 33606
2007-01-28 18:01:49 +00:00
9fa3839d29
More cleanup
...
llvm-svn: 33605
2007-01-28 16:04:40 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
3814e72ed1
Use TargetELFWriterInfo class.
...
llvm-svn: 33573
2007-01-27 02:55:44 +00:00
f209495e93
Handle multiple functions, properly mangle symbols, and fix support for
...
scattered relocations.
llvm-svn: 33555
2007-01-26 22:39:48 +00:00
5a1df9748b
rename files
...
llvm-svn: 33552
2007-01-26 21:38:26 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
f773e14547
Clarify some constants.
...
llvm-svn: 33536
2007-01-26 14:19:17 +00:00
ae4ea45eaf
Added a MRegisterInfo hook that tells PEI the target is responsible for
...
rounding the stack frame to a multiple of stack alignment.
llvm-svn: 33504
2007-01-25 22:12:41 +00:00
ee132b5fce
1. Remove dwarf-verbose option (now asm-verbose.)
...
2. Clean up end of lines.
llvm-svn: 33499
2007-01-25 15:45:58 +00:00
1c055e8d14
Migrate print routines to asm to be shared by exception handling.
...
llvm-svn: 33498
2007-01-25 15:12:02 +00:00
f6c63fec92
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
...
by value so that clean up is less confusing (these vectors tend to be small.)
llvm-svn: 33488
2007-01-24 18:45:13 +00:00
f6487ec894
Use asm printer to emit alignment
...
llvm-svn: 33485
2007-01-24 13:12:32 +00:00
06a03210af
Make ivars private and use getters. Have the MachOWriter return "Mach-O
...
Writer" for the pass name.
llvm-svn: 33483
2007-01-24 07:13:56 +00:00
f5c96fabf9
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
...
llvm-svn: 33482
2007-01-24 07:03:39 +00:00
4905a473e8
Use the TargetMachOWriterInfo class to get this information.
...
llvm-svn: 33478
2007-01-24 03:38:47 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
...
llvm-svn: 33460
2007-01-23 09:38:11 +00:00
199818475b
Switch this to use SmallSet to avoid mallocs in the common case.
...
llvm-svn: 33457
2007-01-23 00:59:48 +00:00
d39e38848b
Fix a bunch of inline asm failures
...
llvm-svn: 33454
2007-01-23 00:36:17 +00:00
be48a47d9d
Remove the DoubleTy special case.
...
llvm-svn: 33449
2007-01-22 23:13:55 +00:00
2eadb5310d
For PR970:
...
Clean up handling of isFloatingPoint() and dealing with PackedType.
Patch by Gordon Henriksen!
llvm-svn: 33415
2007-01-21 00:29:26 +00:00
50ee0e40e5
Teach TargetData to handle 'preferred' alignment for each target, and use
...
these alignment amounts to align scalars when we can. Patch by Scott Michel!
llvm-svn: 33409
2007-01-20 22:35:55 +00:00
00a640dbe0
Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.
...
llvm-svn: 33398
2007-01-20 10:10:26 +00:00
887f75ac0a
Remove an unused variable.
...
llvm-svn: 33396
2007-01-20 09:21:54 +00:00
7ab6fa3a67
We not align the final stack slot but instead let the target do so in emitPrologue(). Each target can make adjustments to the stack frame and re-align the stack as it deem appropriate. Do not align it twice which can end up wasting stack space.
...
llvm-svn: 33387
2007-01-20 02:07:13 +00:00
fc74e2de26
GetRegForReload() now keeps track which registers have been considered and rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this:
...
t1 := op t2, t3
t2 <- assigned r0 for use by the reload but ended up reuse r1
t3 <- assigned r1 for use by the reload but ended up reuse r0
t1 <- desires r1
sees r1 is taken by t2, tries t2's reload register r0
sees r0 is taken by t3, tries t3's reload register r1
sees r1 is taken by t2, tries t2's reload register r0 ...
llvm-svn: 33382
2007-01-19 22:40:14 +00:00
a94d394ad2
For PR1043:
...
This is the final patch for this PR. It implements some minor cleanup
in the use of IntegerType, to wit:
1. Type::getIntegerTypeMask -> IntegerType::getBitMask
2. Type::Int*Ty changed to IntegerType* from Type*
3. ConstantInt::getType() returns IntegerType* now, not Type*
This also fixes PR1120.
Patch by Sheng Zhou.
llvm-svn: 33370
2007-01-19 21:13:56 +00:00
9201100b29
Remove this xform:
...
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
Replace it with:
(add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
This fixes test/CodeGen/ARM/smul.ll
llvm-svn: 33361
2007-01-19 17:51:44 +00:00
e750f61ac5
Have the OutputBuffer take the is64Bit and isLittleEndian booleans.
...
llvm-svn: 33316
2007-01-18 01:23:11 +00:00
0ee2d46cfe
add new JumpTableSpecialLabelPrefix hook to asmprinter for jumptable emission.
...
llvm-svn: 33314
2007-01-18 01:12:56 +00:00
cd9c1f035a
Changed to use the OutputBuffer instead of the methods in MachO and ELF
...
writers.
llvm-svn: 33311
2007-01-17 22:22:31 +00:00
38ee6519b7
Revert patch.
...
llvm-svn: 33298
2007-01-17 09:06:13 +00:00
dcc324b15b
Use the methods in the TargetObjInfo object instead of internal methods.
...
llvm-svn: 33289
2007-01-17 03:49:21 +00:00
4dc4489286
Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by being
...
careful when folding "c ? load p : load q" that C doesn't reach either load.
If so, folding this into load (c ? p : q) will induce a cycle in the graph.
llvm-svn: 33251
2007-01-16 05:59:59 +00:00
f70c5cd5db
add options to view the dags before the first or second pass of dag combine.
...
llvm-svn: 33249
2007-01-16 04:55:25 +00:00
e21237e59a
Fix for PR1095:
...
LLVM would miscompile ASM dialects when compiling for PPC. Added dialects for
the X86 and PPC backends. It defaults to "0", the first variant of a compound
inline asm expression.
llvm-svn: 33246
2007-01-16 03:42:04 +00:00
03c4953cdd
rename Type::isIntegral to Type::isInteger, eliminating the old Type::isInteger.
...
rename Type::getIntegralTypeMask to Type::getIntegerTypeMask.
This makes naming much more consistent. For example, there are now no longer any
instances of IntegerType that are not considered isInteger! :)
llvm-svn: 33225
2007-01-15 02:27:26 +00:00
c69c6c4db2
eliminate calls to Type::isInteger, preferring isIntegral instead.
...
llvm-svn: 33222
2007-01-15 02:03:16 +00:00
a8a0f2cf68
Compensate for loss of DerivedTypes.h in TargetLowering.h
...
llvm-svn: 33159
2007-01-12 23:31:12 +00:00
ddf1421b8e
Move a function out of line.
...
llvm-svn: 33158
2007-01-12 23:30:31 +00:00
61a4be88b4
Minor fix.
...
llvm-svn: 33149
2007-01-12 22:51:10 +00:00
7f6fac4bb5
Simplify code
...
llvm-svn: 33123
2007-01-12 18:15:09 +00:00
7a9c62baa6
For PR1064:
...
Implement the arbitrary bit-width integer feature. The feature allows
integers of any bitwidth (up to 64) to be defined instead of just 1, 8,
16, 32, and 64 bit integers.
This change does several things:
1. Introduces a new Derived Type, IntegerType, to represent the number of
bits in an integer. The Type classes SubclassData field is used to
store the number of bits. This allows 2^23 bits in an integer type.
2. Removes the five integer Type::TypeID values for the 1, 8, 16, 32 and
64-bit integers. These are replaced with just IntegerType which is not
a primitive any more.
3. Adjust the rest of LLVM to account for this change.
Note that while this incremental change lays the foundation for arbitrary
bit-width integers, LLVM has not yet been converted to actually deal with
them in any significant way. Most optimization passes, for example, will
still only deal with the byte-width integer types. Future increments
will rectify this situation.
llvm-svn: 33113
2007-01-12 07:05:14 +00:00
cddc9dfe97
Implement review feedback for the ConstantBool->ConstantInt merge. Chris
...
recommended that getBoolValue be replaced with getZExtValue and that
get(bool) be replaced by get(const Type*, uint64_t). This implements
those changes.
llvm-svn: 33110
2007-01-12 04:24:46 +00:00
31cbddf28a
Store default libgcc routine names and allow them to be redefined by target.
...
llvm-svn: 33105
2007-01-12 02:11:51 +00:00
542964f55b
Rename BoolTy as Int1Ty. Patch by Sheng Zhou.
...
llvm-svn: 33076
2007-01-11 18:21:29 +00:00
75b871fb1e
For PR1043:
...
Merge ConstantIntegral and ConstantBool into ConstantInt.
Remove ConstantIntegral and ConstantBool from LLVM.
llvm-svn: 33073
2007-01-11 12:24:14 +00:00
6730f03370
Naming consistency.
...
llvm-svn: 33026
2007-01-08 23:55:53 +00:00
961bbd393b
Fix for PR1075: bottom-up register-reduction scheduling actually increases register pressure.
...
- Fixed bugs in sethi-ullman number computation and priority queue comparison
functions.
- Separate code that handles priority computation special cases from SU number computation.
llvm-svn: 33025
2007-01-08 23:50:38 +00:00
0199fd6d59
Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.
...
This implements CodeGen/PowerPC/unsafe-math.ll
llvm-svn: 33024
2007-01-08 23:04:05 +00:00
3106724a03
Need to handle static declarations properly.
...
llvm-svn: 33022
2007-01-08 22:15:18 +00:00
2a116abf3a
llvm 2.0 doesn't support llvm.isunordered.*
...
llvm-svn: 32994
2007-01-07 08:52:43 +00:00
10cae15d8e
remove support for llvm.isunordered
...
llvm-svn: 32992
2007-01-07 08:37:22 +00:00
34acba48cc
Change the interface to Module::getOrInsertFunction to be easier to use,to resolve PR1088, and to help PR411.
...
This simplifies many clients also
llvm-svn: 32989
2007-01-07 08:12:01 +00:00
5f80c450f3
Expand fcopysign to the bitwise sequence if select is marked as expensive.
...
llvm-svn: 32940
2007-01-05 23:33:44 +00:00
3b841ddbe0
Bug in ExpandFCOPYSIGNToBitwiseOps(). Clear the old sign bit of operand 0
...
before or'ing in the sign bit of operand 1.
llvm-svn: 32930
2007-01-05 21:31:51 +00:00
376c9c4c97
CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg.
...
llvm-svn: 32929
2007-01-05 20:59:06 +00:00
8ec5283dc4
GEP subscript is interpreted as a signed value.
...
llvm-svn: 32888
2007-01-05 01:46:20 +00:00
96035bed51
fix PowerPC/2007-01-04-ArgExtension.ll, a bug handling K&R prototypes with
...
the recent signless changes.
llvm-svn: 32884
2007-01-04 22:22:37 +00:00
003feb03d5
Expand fcopysign to a series of bitwise of operations when it's profitable to
...
do so.
llvm-svn: 32881
2007-01-04 21:56:39 +00:00
e6f81876eb
Legalizer doesn't do an ANY_EXTEND if we don't ask for one so make sure
...
that we default to an ANY_EXTEND if no parameter attribute is set on the
result value of a function.
llvm-svn: 32836
2007-01-03 16:49:33 +00:00
7601f2f36e
NULL names should pass validation.
...
llvm-svn: 32835
2007-01-03 13:46:20 +00:00
751314fab9
Silence warning.
...
llvm-svn: 32834
2007-01-03 13:36:40 +00:00
2a34b91666
Restore previous behavior of defaulting to ZEXT. This works around two
...
things: (1) preventing PR1071 and (2) working around missing parameter
attributes for bool type. (2) will be fixed shortly. When PR1071 is fixed,
this patch should be undone.
llvm-svn: 32831
2007-01-03 05:03:05 +00:00
0917adf614
Two changes:
...
1. Switch expression and cases are compared signed and are sign extended.
2. For function results needing extended, do SIGN_EXTEND if the SExtAttribute
is set and ZERO_EXTEND if the ZExtAttribute is set, otherwise just let
the Legalizer do ANY_EXTEND.
This fixes the recent regression in kimwitu++ and probably the llvm-gcc
bootstrap issue we had today.
llvm-svn: 32830
2007-01-03 04:25:33 +00:00
791864c6a5
Clean up from recent changes. Comment the new parameter to ExpandLibCall.
...
Consolidate some lines of code and remove duplication.
llvm-svn: 32829
2007-01-03 04:22:32 +00:00
92484c2aa4
- Fixing naming inconsistency: calleesave -> calleesaved.
...
- Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters().
llvm-svn: 32822
2007-01-02 21:31:15 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
266e42b312
For PR950:
...
This patch removes the SetCC instructions and replaces them with the ICmp
and FCmp instructions. The SetCondInst instruction has been removed and
been replaced with ICmpInst and FCmpInst.
llvm-svn: 32751
2006-12-23 06:05:41 +00:00
d7a090ffc4
Need to walk the derived chain of typedefs to get actual size.
...
llvm-svn: 32744
2006-12-22 20:03:42 +00:00
763550323d
Debug dump error.
...
llvm-svn: 32743
2006-12-22 02:04:05 +00:00
4e0c2a0e41
Just print integer constants as signed values. The actual signedness
...
doesn't matter as it is determined in the way the constant is used.
llvm-svn: 32733
2006-12-21 19:04:23 +00:00
6156b02dd3
Simplify all the casting business and get rid of isSigned().
...
llvm-svn: 32731
2006-12-21 08:28:31 +00:00
258657e64e
getLoad() and getStore() calls missed SVOffset operand. Thanks to Dan Gohman
...
for pointing it out!
llvm-svn: 32712
2006-12-20 01:27:29 +00:00
aee775a6b7
Eliminate static ctors from Statistics
...
llvm-svn: 32698
2006-12-19 22:41:21 +00:00
44ef93449a
Fix for PR1059: http://llvm.org/PR1059
...
llvm-svn: 32685
2006-12-19 21:04:20 +00:00
9ad6edf2ec
May need to promote the operand (either sign_extend_inreg or and) before
...
expanding a {s|u}int_to_fp.
llvm-svn: 32665
2006-12-19 01:44:04 +00:00
adc80f98cf
LegalizeSetCCOperands() may end up inserting libcalls. They need to be
...
properly serialized. Do not clear LastCallSEQ_END until that is done.
llvm-svn: 32659
2006-12-18 22:55:34 +00:00
668d90f289
Convert the last uses of CastInst::createInferredCast to a normal cast
...
creation. These changes are still temporary but at least this pushes
knowledge of signedness out closer to where it can be determined properly
and allows signedness to be removed from VMCore.
llvm-svn: 32654
2006-12-18 08:47:13 +00:00
d7998d0e6d
move ExtWeakSymbols to AsmPrinter
...
llvm-svn: 32648
2006-12-18 03:37:18 +00:00
e33ce528da
Fixed so that it dereferences the ostream pointer.
...
llvm-svn: 32640
2006-12-17 11:15:53 +00:00
a77f14265b
Added an automatic cast to "std::ostream*" etc. from OStream. We then can
...
rework the hacks that had us passing OStream in. We pass in std::ostream*
instead, check for null, and then dispatch to the correct print() method.
llvm-svn: 32636
2006-12-17 05:15:13 +00:00
9bd5ed636c
Fix PR1049 and CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
...
by producing target constants instead of constants. Constants can get
selected to li/movri instructions, which causes the scheduler to explode.
llvm-svn: 32633
2006-12-16 21:14:48 +00:00
28cf4277bb
Cannot combine an indexed load / store any further.
...
llvm-svn: 32629
2006-12-16 06:25:23 +00:00
851e589eda
Expand FP undef
...
llvm-svn: 32623
2006-12-16 02:20:50 +00:00
29192e6274
The best unbreakage yet, addressing Bill's concerns.
...
llvm-svn: 32622
2006-12-16 02:15:42 +00:00
860004688a
Allow promoted FP_TO_UINT / FP_TO_SINT to expand operand.
...
llvm-svn: 32621
2006-12-16 02:10:30 +00:00
388cbbf000
Expand fabs / fneg to and / xor.
...
llvm-svn: 32619
2006-12-16 00:52:40 +00:00
b82309f1ab
An even better unbreakage...
...
llvm-svn: 32617
2006-12-15 22:57:14 +00:00
884bc09d10
Fix select_cc, select expansion to soft-fp bugs.
...
llvm-svn: 32616
2006-12-15 22:42:55 +00:00
26df19ace6
This code was usurping the sextload expand in teh legalizer. Just make
...
sure the right conditions are checked.
llvm-svn: 32611
2006-12-15 21:38:30 +00:00
b1a9492ed7
silence a bogus warning
...
llvm-svn: 32597
2006-12-15 07:36:19 +00:00
54c4ab8524
Minor clean up.
...
llvm-svn: 32593
2006-12-15 06:41:01 +00:00
35fdd5ffe1
Expand FP compares to soft-fp call(s)
...
llvm-svn: 32590
2006-12-15 02:59:56 +00:00
70323a8146
1. Tidy up jump table info.
...
2. Allow the jit to handle PIC relocable jump tables.
llvm-svn: 32581
2006-12-14 19:17:33 +00:00
4c306ae0c2
Fix a long-standing spiller bug:
...
If a spillslot value is available in a register, and there is a noop copy that
targets that register, the spiller correctly decide not to invalidate the
spillslot register.
However, even though the noop copy does not clobbers the value. It does start a
new intersecting live range. That means the spillslot register is available for
use but should not be reused for a two-address instruction modref operand which
would clobber the new live range.
When we remove the noop copy, update the available information by clearing the
canClobber bit.
llvm-svn: 32576
2006-12-14 07:54:05 +00:00
22cf89967b
More soft-fp work.
...
llvm-svn: 32559
2006-12-13 20:57:08 +00:00
e370e0eb09
Expand (f64 extload f32) to (f64 fp_ext (load f32)) if f64 type action is expand.
...
llvm-svn: 32527
2006-12-13 03:19:57 +00:00
f3a80c6235
Expand fsqrt, fsin, and fcos to libcalls.
...
llvm-svn: 32526
2006-12-13 02:38:13 +00:00
0a5b805f6d
Expand f32 / f64 to i32 / i64 conversion to soft-fp library calls.
...
llvm-svn: 32523
2006-12-13 01:57:55 +00:00
bfe26ffcfc
Replace CastInst::createInferredCast calls with more accurate cast
...
creation calls.
llvm-svn: 32521
2006-12-13 00:50:17 +00:00
3766fc60da
Expand FP constant to integers if FP types are not legal.
...
llvm-svn: 32497
2006-12-12 22:19:28 +00:00
97a750fc47
Soft fp FNEG, SINT_TO_FP, UINT_TO_FP libcall expansion.
...
llvm-svn: 32495
2006-12-12 21:51:17 +00:00
47833a1d28
Expand ConstantFP to load from CP if float types are being expanded.
...
llvm-svn: 32494
2006-12-12 21:32:44 +00:00
634885f71e
Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.
...
llvm-svn: 32493
2006-12-12 21:21:32 +00:00
0076ca0da9
- When expanding a bit_convert whose src operand is also to be expanded and
...
its expansion result type is equal to the result type of the bit_convert,
e.g. (i64 bit_convert (f64 op)) if FP is not legal
returns the result of the expanded source operand.
- Store f32 / f64 may be expanded to a single store i32/i64.
llvm-svn: 32490
2006-12-12 19:53:13 +00:00
0c0b78c18e
Expand formal arguments and call arguments recursively: e.g. f64 -> i64 -> 2 x i32.
...
llvm-svn: 32476
2006-12-12 07:27:38 +00:00
2f96e7d241
fit in 80 cols
...
llvm-svn: 32474
2006-12-12 05:22:21 +00:00
080881614d
this can only be fptrunc.
...
llvm-svn: 32473
2006-12-12 05:21:51 +00:00
6801f02557
This case isn't needed with recent changes to ConstantInt::get
...
llvm-svn: 32472
2006-12-12 05:19:46 +00:00
0c537dae55
split up inttoptr from ptrtoint handling, the cases aren't similar at all.
...
llvm-svn: 32471
2006-12-12 05:18:19 +00:00
b9e41f5559
the operand of a bitcast is always the right size, just emit it in place.
...
llvm-svn: 32470
2006-12-12 05:14:13 +00:00
6ba11fbd75
Revert Nate's patch to fix X86/store-fp-constant.ll. With the dag combiner
...
and legalizer separated like they currently are, I don't see a way to handle
this xform.
llvm-svn: 32466
2006-12-12 04:18:56 +00:00
b7524b6d0e
make this code more aggressive about turning store fpimm into store int imm.
...
This is not sufficient to fix X86/store-fp-constant.ll
llvm-svn: 32465
2006-12-12 04:16:14 +00:00
38dbe1ca14
Tidy up a bit.
...
llvm-svn: 32462
2006-12-12 01:32:02 +00:00
3c49edcaa1
Change inferred cast creation calls to more specific cast creations.
...
llvm-svn: 32460
2006-12-12 01:17:41 +00:00
3432ab97c1
Re-apply changes that were backed out and fix a naughty typo.
...
llvm-svn: 32442
2006-12-11 19:27:14 +00:00
b3b285185f
It seems the llvm::OStream class does not handle stream manipulators.
...
For now, just grab the stream and perform the output on it directly.
llvm-svn: 32441
2006-12-11 19:15:36 +00:00
e9a203c4e5
Revert changes that broke oggenc on ppc
...
llvm-svn: 32440
2006-12-11 18:53:38 +00:00
218369881f
Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal type.
...
llvm-svn: 32434
2006-12-11 17:25:19 +00:00
f4bec95b58
f32 / f64 node is expanded to one i32 / i64 node.
...
llvm-svn: 32433
2006-12-11 06:50:04 +00:00
f6b01fdb48
Clean up some bad code.
...
llvm-svn: 32432
2006-12-11 06:25:26 +00:00
8e20c760fa
Move something that should be in the dag combiner from the legalizer to the
...
dag combiner.
llvm-svn: 32431
2006-12-11 02:23:46 +00:00
e8da58b3f9
Properly mangles symbol table names
...
Supports constant pools
Supports relocations to jump tables
Supports relocations within the data segment (global = address of global)
Allocates memory in a non-hacky for all non-code objects.
llvm-svn: 32430
2006-12-11 02:20:45 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
4eee72471c
Preliminary soft float support.
...
llvm-svn: 32394
2006-12-09 02:42:38 +00:00
78cb08d082
Move findTiedToSrcOperand to TargetInstrDescriptor.
...
llvm-svn: 32366
2006-12-08 18:45:48 +00:00
bb4e6d4d12
Proper fix for PR1037: to determine is a VR is a modref, check 1) whether it is
...
tied to another oeprand, 2) whether is is being tied to by another operand. So
the destination operand of a two-address MI can be correctly identified.
llvm-svn: 32354
2006-12-08 08:02:34 +00:00
4539418a7b
findTiedToSrcOperand() changed.
...
llvm-svn: 32353
2006-12-08 07:59:51 +00:00
d9f04e4875
Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64
...
llvm-svn: 32336
2006-12-07 22:36:47 +00:00
355fc5ad50
Removed more <iostream> includes
...
llvm-svn: 32321
2006-12-07 20:28:15 +00:00
22e978a736
Removing even more <iostream> includes.
...
llvm-svn: 32320
2006-12-07 20:04:42 +00:00
e44aa812b4
Revision 1.83 causes PR1037.
...
Reverted.
llvm-svn: 32305
2006-12-07 16:21:19 +00:00
c41ed4e0e1
Initialize {Min|Max}CSFrameIndex properly.
...
llvm-svn: 32299
2006-12-07 02:25:34 +00:00
f3baad3ee1
Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, are
...
now cerr, cout, and NullStream resp.
llvm-svn: 32298
2006-12-07 01:30:32 +00:00
e312c152d2
MI keeps a ptr of TargetInstrDescriptor, use it.
...
llvm-svn: 32296
2006-12-07 01:21:59 +00:00
7074cbd449
getOperandConstraint returns -1 if the operand does have the specific constraint. This bug was causing excessive spills.
...
llvm-svn: 32295
2006-12-07 00:46:04 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
acbb456dde
Some addresssed should be 64-bit and some shouldn't.
...
llvm-svn: 32278
2006-12-06 17:43:18 +00:00
75c2194b1a
Move copyKillDeadInfo out-of-line. Add findRegisterUseOperand().
...
llvm-svn: 32273
2006-12-06 08:27:42 +00:00
979804d800
eliminate fp statistic
...
llvm-svn: 32251
2006-12-06 01:48:55 +00:00
cc08c83186
Unbreak VC++ build.
...
llvm-svn: 32113
2006-12-02 02:22:01 +00:00
67fc141db5
Match TargetInstrInfo changes.
...
llvm-svn: 32098
2006-12-01 21:52:58 +00:00
f52337299a
better check for version
...
llvm-svn: 32045
2006-11-30 18:29:23 +00:00
b5b14060a8
Change global descriptor names to provide name, full name and linkage name.
...
llvm-svn: 32036
2006-11-30 14:35:45 +00:00
aa2843ad4a
Temp fix to deal gdb issue.
...
llvm-svn: 32035
2006-11-30 11:09:42 +00:00
3c3ce98530
- MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode.
...
- Remove the ugly TargetInstrDescriptors hack.
llvm-svn: 32032
2006-11-30 07:08:44 +00:00
a743fada65
Avoid inifinite looping if READCYCLECOUNTER isn't custom lowered.
...
llvm-svn: 32022
2006-11-29 19:13:47 +00:00
01b74b6f7b
Eliminate unnecessary scopes.
...
llvm-svn: 32020
2006-11-29 16:55:57 +00:00
6973993e9c
Allow target to custom lower READCYCLECOUNTER (when it doesn't have to be expanded).
...
llvm-svn: 32016
2006-11-29 08:26:18 +00:00
feba507a97
Fix for PR1023 by Dan Gohman.
...
llvm-svn: 32003
2006-11-29 01:58:12 +00:00
6e12a052ff
Fix for PR1022 (folding loads of static initializers) by Dan Gohman.
...
llvm-svn: 32000
2006-11-29 01:38:07 +00:00
90f4238c38
add a hook to allow targets to hack on inline asms to lower them to llvm
...
when they want to.
llvm-svn: 31997
2006-11-29 01:12:32 +00:00
5c3966aa68
Converted to using llvm streams instead of <iostream>s
...
llvm-svn: 31992
2006-11-29 00:39:47 +00:00
787b77320f
Use llvm streams instead of <iostream>
...
llvm-svn: 31985
2006-11-28 22:48:48 +00:00
bc0d5f8bcb
Put the #include for a module first.
...
llvm-svn: 31958
2006-11-28 03:31:29 +00:00
b2a6b0dbad
Clean up.
...
llvm-svn: 31957
2006-11-28 02:25:34 +00:00
3f6f0fd028
Changed to using llvm streams.
...
llvm-svn: 31954
2006-11-28 02:08:17 +00:00
3abb63651b
Fix PR1016
...
llvm-svn: 31950
2006-11-28 01:03:30 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5d5916b4d1
Fix the dag combiner bug corresponding to PR1014.
...
llvm-svn: 31943
2006-11-27 21:50:02 +00:00
3da631f29a
For better or worse, load from i1 is assumed to be zero extended. Do not
...
form a load from i1 from larger loads that may not be zext'd.
llvm-svn: 31933
2006-11-27 04:40:53 +00:00
db18938355
If a brcond condition is promoted, make sure to zero extend it, even if not
...
expanded into BR_CC.
llvm-svn: 31932
2006-11-27 04:39:56 +00:00
6c38f0bb07
For PR950:
...
The long awaited CAST patch. This introduces 12 new instructions into LLVM
to replace the cast instruction. Corresponding changes throughout LLVM are
provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the
exception of 175.vpr which fails only on a slight floating point output
difference.
llvm-svn: 31931
2006-11-27 01:05:10 +00:00
d7f53cdaec
Global label not handled correctly.
...
llvm-svn: 31883
2006-11-20 20:29:06 +00:00
3676a994ca
Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
...
llvm-svn: 31878
2006-11-20 18:05:46 +00:00
539df43e4b
setOperand should not zap the operand list or add implicit operands to an
...
instruction. Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.
This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll
llvm-svn: 31876
2006-11-20 17:57:22 +00:00
d9436b6837
For PR950:
...
First in a series of patches to convert SetCondInst into ICmpInst and
FCmpInst using only two opcodes and having the instructions contain their
predicate value. Nothing uses these classes yet. More patches to follow.
llvm-svn: 31867
2006-11-20 01:22:35 +00:00
ea017f66f7
Don't transform in another bad case: if the block is empty, it should be
...
simplified before we do this xform so that our cost model is accurate.
llvm-svn: 31864
2006-11-18 22:25:39 +00:00
56ec81ff73
Fix another case we *don't* want to do this xform.
...
llvm-svn: 31861
2006-11-18 21:56:39 +00:00
ace542fa6c
Implement operator<< for machine basic blocks to make it easier to dump them.
...
llvm-svn: 31857
2006-11-18 21:47:36 +00:00
7acdc17fe4
make the previous change more aggressive, moving any block with no fallthrough.
...
This speeds up yacr2 by 7% on a core2.
llvm-svn: 31856
2006-11-18 21:30:35 +00:00
47ce26158f
Minor code layout tweak: if we have something like this:
...
if (cond) goto BB2
BB1:
...
return;
BB2:
...
Move BB1 to the end of the function so that the code falls through in the
non-return case. This has the effect of moving assert (and other no-return
call) bodies and return blocks out of loops.
llvm-svn: 31855
2006-11-18 20:47:54 +00:00
da0add3fd0
Fixing the ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1 build.
...
llvm-svn: 31822
2006-11-17 13:07:55 +00:00
9d46fcd59c
More removal of std::cerr and DEBUG, replacing with DOUT instead.
...
llvm-svn: 31806
2006-11-17 02:09:07 +00:00
d108b9a60d
Replace std::cerr uses of the "DEBUG" macro with "DOUT" instead. Removes
...
a #include of iostream.
llvm-svn: 31800
2006-11-17 00:50:36 +00:00
8969ebca44
*** empty log message ***
...
llvm-svn: 31789
2006-11-16 20:11:33 +00:00
9fd73b8a7f
Match MachineCodeEmitter changes.
...
llvm-svn: 31787
2006-11-16 20:04:04 +00:00
d811cc6818
Don't recompute getNumOperands for each iteration.
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llvm-svn: 31783
2006-11-16 07:35:18 +00:00
c7969fd1e7
Added a new method "CreateNewLiveInterval" which, given a list of
...
LiveRanges, creates a new LiveInterval from them. The LiveRanges should
have existed already in another LiveInterval, but removed.
llvm-svn: 31780
2006-11-16 02:41:50 +00:00
e0a70388c2
enable the branch folding pass for the JIT.
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llvm-svn: 31777
2006-11-16 01:00:07 +00:00
f64da389f8
Fix an incorrectly inverted condition.
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llvm-svn: 31773
2006-11-16 00:08:20 +00:00
0ffff1c629
Match live variable changes.
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llvm-svn: 31762
2006-11-15 20:55:15 +00:00
ebb0357b4c
Minor updates.
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llvm-svn: 31761
2006-11-15 20:54:29 +00:00
12ea213de9
A register def can be partially dead when the whole register has use(s) but a subreg does not.
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llvm-svn: 31760
2006-11-15 20:54:11 +00:00
70ec52896e
Do away with kill / dead maps. Move kill / dead info onto MI's.
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llvm-svn: 31759
2006-11-15 20:51:59 +00:00
2775aba51d
Simplify IntrinsicLowering and clarify that it is only for use by the
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CBE and interpreter.
llvm-svn: 31755
2006-11-15 18:00:10 +00:00
30d08801ef
remove dead #include
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llvm-svn: 31753
2006-11-15 17:51:15 +00:00
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
77af6ac5e8
- Let MachineInstr ctors add implicit def and use operands. Other operands
...
will be inserted before these operands. If the opcode changes (by
setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
that move kill / dead info to MachineInstr's.
llvm-svn: 31711
2006-11-13 23:34:06 +00:00
2230144a75
Make an assert comment match the tested assertion.
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llvm-svn: 31686
2006-11-11 20:07:59 +00:00
979bbf48d5
Add methods to add implicit def use operands to a MI.
...
llvm-svn: 31675
2006-11-11 10:20:02 +00:00
a0a8003f59
disallow preinc of a frameindex. This is not profitable and causes 2-addr
...
pass to explode. This fixes a bunch of llc-beta failures on ppc last night.
llvm-svn: 31661
2006-11-11 01:00:15 +00:00
eabc15c1d8
reduce indentation by using early exits. No functionality change.
...
llvm-svn: 31660
2006-11-11 00:56:29 +00:00
ffad2166e1
move big chunks of code out-of-line, no functionality change.
...
llvm-svn: 31658
2006-11-11 00:39:41 +00:00
4eac5f59e6
Fix a dag combiner bug exposed by my recent instcombine patch. This fixes
...
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast
llvm-svn: 31644
2006-11-10 21:37:15 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
13440b025c
When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.
...
llvm-svn: 31631
2006-11-10 08:28:11 +00:00
d5e604dbb2
commentate
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llvm-svn: 31627
2006-11-10 04:41:34 +00:00
6878378390
Don't attempt expensive pre-/post- indexed dag combine if target does not support them.
...
llvm-svn: 31598
2006-11-09 19:10:46 +00:00
d550248f2c
Add a mechanism to specify whether a target supports a particular indexed load / store.
...
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
c034f14fbe
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
b15000736c
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
f1606b80f1
Allows debugging llc self hosted.
...
llvm-svn: 31594
2006-11-09 16:32:26 +00:00
97f89b11b3
Merging dwarf info to a single compile unit.
...
llvm-svn: 31593
2006-11-09 14:52:14 +00:00
b58e06bc9e
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
...
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
...
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
85e54223cd
Match more post-indexed ops.
...
llvm-svn: 31569
2006-11-08 20:27:27 +00:00
61feeb90f9
Remove redundant <cmath>.
...
llvm-svn: 31561
2006-11-08 19:16:44 +00:00
62bbc9ef58
Now can re-enable debug label folding.
...
llvm-svn: 31549
2006-11-08 14:17:45 +00:00
0303cb9b33
- When performing pre-/post- indexed load/store transformation, do not worry
...
about whether the new base ptr would be live below the load/store. Let two
address pass split it back to non-indexed ops.
- Minor tweaks / fixes.
llvm-svn: 31544
2006-11-08 08:30:28 +00:00
6072435756
Fixed a minor bug preventing some pre-indexed load / store transformation.
...
llvm-svn: 31543
2006-11-08 06:56:05 +00:00
fdff938a7e
For PR950:
...
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
d48f7dd250
Fix a obscure post-indexed load / store dag combine bug.
...
llvm-svn: 31537
2006-11-08 02:38:55 +00:00
bf3b57f221
optimize single MBB loops better. In particular, produce:
...
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
jne LBB1_57 #bb207.i
jmp LBB1_64 #cond_next255.i
intead of:
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
je LBB1_64 #cond_next255.i
jmp LBB1_57 #bb207.i
This eliminates a branch per iteration of the loop. This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.
llvm-svn: 31530
2006-11-08 01:03:21 +00:00
21d4d895ca
Accidently reran commit.
...
llvm-svn: 31516
2006-11-07 21:58:55 +00:00
a919ba9abd
Missed a label map, reverting till covered.
...
llvm-svn: 31514
2006-11-07 21:37:31 +00:00
21ce53b94e
Missed a label map, reverting till covered.
...
llvm-svn: 31512
2006-11-07 20:53:05 +00:00
6ea4fae838
1. Add a pass to fold debug label instructions so a debug info client can detect
...
empty ranges.
2. Reorg how MachineDebugInfo maintains changes to debug labels.
3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.
4. Revert the merging of compile units until I can get the bugs ironed out.
llvm-svn: 31507
2006-11-07 19:33:46 +00:00
b18177bfab
Enable improved spilling costs by default. This speeds up viterbi on x86
...
by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.
On PPC, this speeds up fourinarow by 18%, and probably other things as well.
llvm-svn: 31504
2006-11-07 18:04:58 +00:00
6a9342166b
Use correct value for float HUGH_VAL.
...
llvm-svn: 31500
2006-11-07 12:25:45 +00:00
60c6846d21
Add post-indexed load / store transformations.
...
llvm-svn: 31498
2006-11-07 09:03:05 +00:00
01d039cc44
Add a new llcbeta option. This speeds up viterbi from 12.34 to 8.76s on
...
X86. If happy, I'll enable this by default.
llvm-svn: 31493
2006-11-07 07:18:40 +00:00
78c84a0328
Unbreak X86/ELF Debugging. Somehow this line got lost in Jim's cleanup.
...
llvm-svn: 31492
2006-11-07 06:36:36 +00:00
94c231f453
Fix PR988 and CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll.
...
The low part goes in the first operand of expandop, not the second one.
llvm-svn: 31487
2006-11-07 04:11:44 +00:00
f24d15f969
Remove dead code; added a missing null ptr check.
...
llvm-svn: 31478
2006-11-06 21:33:46 +00:00
235aeef9e1
Tab interferes with uniqueness.
...
NOTE: There doesn't seem to be consistency for whether a leading tab
is present in a section heading.
llvm-svn: 31475
2006-11-06 16:23:59 +00:00
f39064c2de
D'oh - reversed logic.
...
llvm-svn: 31474
2006-11-06 13:20:29 +00:00
eb99bd736a
Add comment.
...
llvm-svn: 31473
2006-11-06 08:14:30 +00:00
7d6f3db3e2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
33157700d9
Added pre-indexed store support.
...
llvm-svn: 31459
2006-11-05 09:31:14 +00:00
1a1e23eff7
Added getIndexedStore.
...
llvm-svn: 31458
2006-11-05 09:30:09 +00:00
01c55a50b1
Live local variables are being dropped because the begin or end labels marking
...
their scope are being deleted. Workaround is to widen scope to full function.
llvm-svn: 31454
2006-11-04 10:48:07 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
...
llvm-svn: 31453
2006-11-04 09:44:31 +00:00
51733ed4a3
Fixed some spiller bugs exposed by the recent two-address code changes. Now
...
there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.
llvm-svn: 31439
2006-11-04 00:21:55 +00:00
bb3ea2a437
this will work better
...
llvm-svn: 31419
2006-11-03 19:15:55 +00:00
Dan Gohman