llvm-project

Commit Graph

Author	SHA1	Message	Date
Shiva Chen	c3d981aeba	[RISCV] Add new SchedRead SchedWrite The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32, ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64, WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model could use them to describe latency. Differential Revision: https://reviews.llvm.org/D75515	2020-03-10 00:12:27 +08:00
Kai Wang	838a28e234	[RISCV] Scheduler description for the Rocket core Pipeline scheduler model for the RISC-V Rocket micro-architecture using the MIScheduler interface. Support for both 32 and 64-bit Rocket cores is implemented. Differential revision: https://reviews.llvm.org/D68685	2020-01-23 19:36:47 -06:00

Author

SHA1

Message

Date

Shiva Chen

c3d981aeba

[RISCV] Add new SchedRead SchedWrite

The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32,
ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64,
WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model
could use them to describe latency.

Differential Revision: https://reviews.llvm.org/D75515

2020-03-10 00:12:27 +08:00

Kai Wang

838a28e234

[RISCV] Scheduler description for the Rocket core

Pipeline scheduler model for the RISC-V Rocket micro-architecture using the
MIScheduler interface.  Support for both 32 and 64-bit Rocket cores is
implemented.

Differential revision: https://reviews.llvm.org/D68685

2020-01-23 19:36:47 -06:00

2 Commits