llvm-project

Commit Graph

Author	SHA1	Message	Date
Kazushi (Jam) Marukawa	015dee1ac8	[VE] Support (m)0 and (m)1 operands Summary: VE has special operands to represent 0b000...000111...111 (`(m)0`) and 0b111...111000...000 (`(m)1`) bit sequences. This patch supports those operands not only in machine instructions but also in DAG lowering. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D77769	2020-04-09 18:09:00 +02:00
Kazushi (Jam) Marukawa	28a42dd1b9	[VE] Change name of enum to CondCode Summary: Change enum name for condition codes from CondCodes to CondCode. Reviewers: arsenm, simoll, k-ishizaka Reviewed By: arsenm Subscribers: wdng, hiraditya, llvm-commits Tags: #llvm, #ve Differential Revision: https://reviews.llvm.org/D76747	2020-03-25 09:20:05 +01:00
Kazushi (Jam) Marukawa	773ae62ff8	[VE] i64 arguments, return values and constants Summary: Support for i64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72776	2020-01-16 10:09:50 +01:00
Kazushi (Jam) Marukawa	064859bde7	[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598	2020-01-15 09:55:16 +01:00
Kazushi (Jam) Marukawa	00c6e98409	[VE] Target stub for NEC SX-Aurora Summary: This patch registers the 've' target: the NEC SX-Aurora TSUBASA Vector Engine. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D69103	2020-01-09 11:17:35 +01:00

5 Commits