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Commit Graph

Author	SHA1	Message	Date
Kang Zhang	513976df2e	[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118	2020-04-16 16:22:43 +00:00
Qiu Chaofan	4fb99a3330	[PowerPC] Fix ICE when truncating some vectors The legalizer would hit an assertion on PowerPC platform when truncating a vector whose size is not power of 2. This patch is to add a check to prevent vectors with such odd-size elements from being custom lowered. Reviewed By: Hal Finkel Differential Revision: https://reviews.llvm.org/D65261 llvm-svn: 368654	2019-08-13 07:53:29 +00:00

Author

SHA1

Message

Date

Kang Zhang

513976df2e

[PowerPC] Ignore implicit register operands for MCInst

Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118

2020-04-16 16:22:43 +00:00

Qiu Chaofan

4fb99a3330

[PowerPC] Fix ICE when truncating some vectors

The legalizer would hit an assertion on PowerPC platform when truncating
a vector whose size is not power of 2.  This patch is to add a check to
prevent vectors with such odd-size elements from being custom lowered.

Reviewed By: Hal Finkel

Differential Revision: https://reviews.llvm.org/D65261

llvm-svn: 368654

2019-08-13 07:53:29 +00:00

2 Commits