3 Commits

Author	SHA1	Message	Date
Kazushi (Jam) Marukawa	015dee1ac8	[VE] Support (m)0 and (m)1 operands ... Summary: VE has special operands to represent 0b000...000111...111 (`(m)0`) and 0b111...111000...000 (`(m)1`) bit sequences. This patch supports those operands not only in machine instructions but also in DAG lowering. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D77769	2020-04-09 18:09:00 +02:00
Kazushi (Jam) Marukawa	e981a46a77	[VE] Update lea/load/store instructions ... Summary: Modify lea/load/store instructions to accept `disp(index, base)` style addressing mode (called ASX format). Also, uniform the number of DAG nodes to have 3 operands for this ASX format instructions, and update selectADDR functions to lower appropriate MI. Reviewers: arsenm, simoll, k-ishizaka Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D76822	2020-04-06 11:49:46 +02:00
Kazushi (Jam) Marukawa	6b587ee23c	[VE] Isel patterns for fp32/64 and i32/64 conversion ... Summary: fp32/64 <> signed/unsigned i32/64 conversion isel patterns and tests (This patch depends on `fsub` implemented by https://reviews.llvm.org/D73540 ) Reviewers: arsenm, craig.topper, rengolin, k-ishizaka Reviewed By: arsenm Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits Tags: #ve, #llvm Differential Revision: https://reviews.llvm.org/D73544	2020-01-29 14:10:22 +01:00