49e14432c2
Make the write*map methods more self-contained. Document some more.
...
llvm-svn: 6589
2003-06-03 19:30:15 +00:00
71ab329f08
I documented this file, in an attempt to understand it, with a view toward
...
rewriting it. I also vacuumed out all the commented-out code and
inaccurate comments, etc.
(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)
llvm-svn: 6574
2003-06-03 07:56:05 +00:00
0521493aa9
Use the new -o tablegen option
...
llvm-svn: 6572
2003-06-03 05:06:33 +00:00
2712333e5f
Constants are laid out in memory in PC-relative form.
...
llvm-svn: 6568
2003-06-03 03:24:12 +00:00
c8728a147e
Added opcode conversion for conditional move of integers.
...
llvm-svn: 6567
2003-06-03 03:23:35 +00:00
cdf6256940
* Convert load/store opcodes from register to immediate forms.
...
* Stop code from wrapping to the next line.
llvm-svn: 6566
2003-06-03 03:21:58 +00:00
3cdf52a644
Convert load/store opcodes from register to immediate forms, if necessary.
...
llvm-svn: 6565
2003-06-03 03:20:57 +00:00
b54bf54065
Store instructions are different from other Format 3.1/3.2 instructions in that
...
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
llvm-svn: 6564
2003-06-03 03:20:14 +00:00
bbd10f96a2
* Added section A.34: Move FP register on int reg condition (FMOVr)
...
* Labeled sections that are not currently used in the Sparc backend as not
requiring completion at this time.
llvm-svn: 6562
2003-06-03 01:16:27 +00:00
e9465fc1d4
* Removed unused classes (rd field is always mentioned last); fixed comments.
...
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
llvm-svn: 6561
2003-06-03 01:13:53 +00:00
ace89ff224
* Removed unused classes: the rd field is always mentioned as the last reg.
...
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
llvm-svn: 6560
2003-06-03 01:11:58 +00:00
4485c795a9
The rd field goes after the immediate field in format 2.1 instructions.
...
llvm-svn: 6559
2003-06-03 01:04:04 +00:00
f545b2402f
Added MOVR (move int reg on register condition), aka comparison with zero.
...
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.
llvm-svn: 6549
2003-06-02 21:16:54 +00:00
843d6933a0
SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions
...
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
llvm-svn: 6548
2003-06-02 20:55:14 +00:00
609b55c255
* Added casts to/from floating-point to integers.
...
* Changed // comments to #ifdef 0 to maintain syntax highlighting.
llvm-svn: 6546
2003-06-02 19:08:37 +00:00
55c6331637
Clean up after merging in SparcEmitter.cpp; branches and return work again.
...
llvm-svn: 6536
2003-06-02 05:24:46 +00:00
ce62d36615
Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver taken
...
from lib/Target/X86/X86CodeEmitter.cpp .
llvm-svn: 6530
2003-06-02 04:12:39 +00:00
bca71e4735
Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue().
...
llvm-svn: 6522
2003-06-02 02:13:26 +00:00
13dffdefef
Make the .inc file depend on $(TBLGEN), so that changes to TableGen followed
...
by a re-link of TableGen will notify Make to rebuild the .inc file.
llvm-svn: 6512
2003-06-01 04:52:51 +00:00
e6c3ee6b07
Add map info for arguments to call (copies)
...
llvm-svn: 6503
2003-06-01 02:48:23 +00:00
ba6f8e274a
Several bug fixes: globals in call operands were not being pulled out;
...
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.
llvm-svn: 6466
2003-05-31 07:34:57 +00:00
a83804a29a
Extensive changes to the way code generation occurs for function
...
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
2003-05-31 07:32:01 +00:00
96b801ab56
Reverting previous beautification changes.
...
llvm-svn: 6464
2003-05-31 07:27:17 +00:00
bf69b7fe69
Removed useless code -- the byte order of output code is correct as is.
...
llvm-svn: 6462
2003-05-31 06:26:06 +00:00
23937091f0
The 'rd' register is consistently mentioned last in instruction definitions.
...
Created new classes from which instructions inherit their ordering of fields.
llvm-svn: 6461
2003-05-31 06:25:19 +00:00
c4f029f8ba
* Put back into action SLL/SRL/SRA{r,i}6 instructions
...
* Fixed page numbers referring to the Sparc manual
llvm-svn: 6460
2003-05-31 06:24:29 +00:00
8d5316769f
Code beautification, no functional changes.
...
llvm-svn: 6459
2003-05-31 06:22:37 +00:00
0b3a70c25b
Enabling some of these passes causes lli to break
...
llvm-svn: 6457
2003-05-31 04:23:04 +00:00
87cbd97710
The actual order of parameters in a 2-reg-immediate assembly instructions is
...
"rs1, imm, rd": most importantly, rd goes last.
llvm-svn: 6456
2003-05-31 04:22:26 +00:00
5bf351c880
Added:
...
* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers
llvm-svn: 6449
2003-05-30 20:17:33 +00:00
0757de607a
Fixed the namespace to match SparcInternals.h; added notes on some missing
...
sections of instructions.
llvm-svn: 6448
2003-05-30 20:15:59 +00:00
8747377292
The register types need to be visible outside of the class to be useful.
...
For one, converting register numbers based on class in the code emitter.
llvm-svn: 6447
2003-05-30 20:12:42 +00:00
a853af587a
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
...
Code beautification for the rest of the code: changed layout to match the rest
of the code base.
llvm-svn: 6446
2003-05-30 20:11:56 +00:00
c1830a472a
Make LLI behave just like LLC with regard to the compile passes it uses.
...
llvm-svn: 6444
2003-05-30 20:00:13 +00:00
39dfa6a920
Made the register and immediate versions of instructions consecutive.
...
llvm-svn: 6439
2003-05-30 19:14:01 +00:00
f6e4dce74c
Because the format of the shift instructions is `shift r, shcnt, r', the
...
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.
Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.
The other changes are just elimination of unnecessary spaces.
llvm-svn: 6437
2003-05-30 18:06:10 +00:00
d380f29377
Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
...
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
llvm-svn: 6429
2003-05-30 08:02:14 +00:00
6ada87e6eb
Since there is now another derived .inc file, ignore them all.
...
llvm-svn: 6411
2003-05-29 20:15:27 +00:00
9175a5de53
Use an absolute path to TableGen because not everyone (e.g. automatic tester)
...
has their path set up by this point.
llvm-svn: 6410
2003-05-29 20:09:56 +00:00
35d5512f34
When TableGen finds an error in the SparcV9.td file, it exits with a non-zero
...
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.
Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.
llvm-svn: 6392
2003-05-29 05:29:22 +00:00
794c8a1334
Fixed to use the correct format of the instruction.
...
llvm-svn: 6390
2003-05-29 04:53:56 +00:00
376dac2eed
This should work better with re-generating the SparcV9CodeEmitter.inc file.
...
Also, added a rule to delete the generated .inc file on `make clean'.
llvm-svn: 6389
2003-05-29 03:32:49 +00:00
ea4f498395
* Broke up SparcV9.td into separate files as it was getting unmanageable
...
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
llvm-svn: 6388
2003-05-29 03:31:43 +00:00
fded35952a
Fixed ordering of elements in instructions: although the binary instructions
...
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
2003-05-28 17:49:29 +00:00
2c35144ce5
Add dependency to make TableGen rule fire.
...
llvm-svn: 6383
2003-05-28 17:41:09 +00:00
07b60f8e2e
Fixed an error preventing compilation.
...
llvm-svn: 6381
2003-05-27 22:48:28 +00:00
481dfdb523
Added the 'r' and 'i' annotations to instructions as their opcode names have
...
changed.
llvm-svn: 6380
2003-05-27 22:44:44 +00:00
7975661a8e
Keep track of the current BasicBlock being processed so that a referencing
...
MachineInstr can later be patched up correctly.
llvm-svn: 6378
2003-05-27 22:41:44 +00:00
af96d39c04
Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.
...
llvm-svn: 6377
2003-05-27 22:40:34 +00:00
96ce62a105
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.
llvm-svn: 6376
2003-05-27 22:39:01 +00:00
da83883ef1
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
llvm-svn: 6375
2003-05-27 22:37:00 +00:00
8bde6a688c
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
llvm-svn: 6373
2003-05-27 22:35:43 +00:00
cb801a6884
Added entries for each of the instructions with annotations ('r' or 'i').
...
llvm-svn: 6372
2003-05-27 22:33:39 +00:00
db69bebc89
One of the first major changes to make the work of JITting easier: adding
...
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
llvm-svn: 6371
2003-05-27 22:32:38 +00:00
8110439ff6
* Allow passing in an unsigned configuration to allocateSparcTargetMachine()
...
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes
llvm-svn: 6369
2003-05-27 22:24:48 +00:00
8b28140662
Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile so
...
that Makefile.common would see it.
llvm-svn: 6367
2003-05-27 22:04:38 +00:00
5641434438
Add prototypes to add passes to JIT compilation and code emission.
...
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.
llvm-svn: 6366
2003-05-27 22:01:10 +00:00
e195b7c0fc
Broke out class definition from SparcV9CodeEmitter, and added ability to take a
...
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.
llvm-svn: 6363
2003-05-27 21:45:05 +00:00
3e9272fb29
SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main function
...
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).
Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .
llvm-svn: 6357
2003-05-27 20:07:58 +00:00
d452b60678
Added definitions for a bunch of floating-point instructions.
...
llvm-svn: 6356
2003-05-27 20:03:29 +00:00
8adb9944aa
Added special register class containing (for now) %fsr.
...
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
2003-05-27 00:02:22 +00:00
3ee4e2a3c1
Bug fix: right shift for int divide-by-power-of-2 was incorrect for
...
negative values. Need to add one to a negative value before right shift!
llvm-svn: 6334
2003-05-25 21:59:47 +00:00
5f36d741db
Bug fix: padding bytes within a structure should go after each field!
...
llvm-svn: 6333
2003-05-25 21:59:09 +00:00
5b941461b1
Bug fix: sign-extension was not happening for C = -MININT since C == -C!
...
llvm-svn: 6332
2003-05-25 21:58:11 +00:00
c9a0a1d728
Add support for compiling varargs functions.
...
llvm-svn: 6325
2003-05-25 15:59:47 +00:00
e2402c65d0
Reword to remove reference to how things worked in the past.
...
llvm-svn: 6323
2003-05-24 01:08:43 +00:00
d21a02ad58
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.
...
llvm-svn: 6320
2003-05-24 00:09:50 +00:00
39968bbc46
Cleaned up code layout; no functional changes.
...
llvm-svn: 6312
2003-05-23 19:20:57 +00:00
c42dc745db
Fixed `volatile' typo.
...
llvm-svn: 6266
2003-05-21 19:34:28 +00:00
f865cc44ab
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6265
2003-05-21 18:48:06 +00:00
2a651d7a0e
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6262
2003-05-21 18:05:35 +00:00
352f7ac072
Namespacified `vector' and `cerr' to always use the `std::' namespace.
...
Eliminated `using' directives.
llvm-svn: 6261
2003-05-21 17:59:06 +00:00
56f4fa10fd
Sparc instruction opcodes now all live under the `V9' namespace.
...
llvm-svn: 6249
2003-05-20 20:32:24 +00:00
b1eee00034
Remove wierd printout
...
llvm-svn: 6145
2003-05-12 20:10:12 +00:00
25e907dae4
Added the initial version of the TableGen description for the Sparc backend.
...
llvm-svn: 6021
2003-05-07 21:52:39 +00:00
3ed86610cd
Eliminate use of NonCopyable so that doxygen documentation doesn't link
...
the Annotation classes with the noncopyable classes for no reason
llvm-svn: 5973
2003-05-01 20:28:45 +00:00
4f6cdbdf81
Remove two fields from TargetData which are target specific.
...
llvm-svn: 5963
2003-04-26 20:11:09 +00:00
21d4509d76
IntegerRegSize is always 8 for sparc
...
llvm-svn: 5961
2003-04-26 19:44:35 +00:00
efbae9cff1
Fix obvious type-o
...
llvm-svn: 5932
2003-04-25 05:23:10 +00:00
13cafd041a
Trivial cleanup
...
llvm-svn: 5899
2003-04-24 18:35:51 +00:00
524608ab79
Add support for the Switch instruction by running the lowerSwitch pass first
...
llvm-svn: 5867
2003-04-23 16:24:55 +00:00
379a8d2d1c
Add new linkage types to support a real frontend
...
llvm-svn: 5786
2003-04-16 20:28:45 +00:00
dea36ca100
Move sparc specific code into the Sparc backend
...
llvm-svn: 5317
2003-01-15 21:36:50 +00:00
4f596d7a2c
Fix warnings
...
llvm-svn: 5316
2003-01-15 21:36:30 +00:00
f9fd59148c
Adjust to simpler interfaces
...
Eliminate dependency on RegClass.h
llvm-svn: 5315
2003-01-15 21:14:32 +00:00
a23969b669
#include RegClass.h explicitly
...
llvm-svn: 5307
2003-01-15 19:57:07 +00:00
90fc665489
Move private header to private directory
...
llvm-svn: 5305
2003-01-15 19:50:44 +00:00
d840ccd2e0
Prune #includes
...
llvm-svn: 5303
2003-01-15 19:48:13 +00:00
e58cd301cd
Use BuildMI more
...
llvm-svn: 5299
2003-01-15 19:23:34 +00:00
8145abb99e
Fix bug found by regtests
...
llvm-svn: 5294
2003-01-15 18:11:11 +00:00
1ebaa90f48
Use BuildMI more, Create*Instruction less
...
llvm-svn: 5291
2003-01-15 17:47:49 +00:00
71aa7afc27
* Elimiante a bunch of functions from InstrSelectionSupport.h, replacing users
...
of them with BUildMI calls instead.
* Fix def information in instructions generated by prologepilog inserter
llvm-svn: 5287
2003-01-15 00:03:28 +00:00
24c1d5e551
Rename llvm/Analysis/LiveVar/FunctionLiveVarInfo.h -> llvm/CodeGen/FunctionLiveVarInfo.h
...
llvm-svn: 5284
2003-01-14 23:05:08 +00:00
b4d58d7f9e
Rename MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5272
2003-01-14 22:00:31 +00:00
c49ca9ce58
Minor cleanups
...
llvm-svn: 5266
2003-01-14 20:32:10 +00:00
f9781b59ab
More renamings of Target/Machine*Info to Target/Target*Info
...
llvm-svn: 5204
2002-12-29 03:13:05 +00:00
42d59219c7
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5203
2002-12-29 02:50:35 +00:00
83d835da2a
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5202
2002-12-29 02:50:33 +00:00
871e591e34
Rename MachineFrameInfo to TargetFrameInfo.h
...
llvm-svn: 5199
2002-12-28 21:00:25 +00:00
2ca5e23403
Put class in anonymous namespace
...
llvm-svn: 5197
2002-12-28 20:42:56 +00:00
d47aac9d4b
* Rename machineFrameInfo to targetFrameInfo
...
* Constant pool and frame info is no longer directly in MachineFunction
llvm-svn: 5177
2002-12-28 20:21:29 +00:00
fe9b705bed
* Rename MachineFrameInfo to TargetFrameInfo
...
* Move some sparc specific code here from Target files
llvm-svn: 5176
2002-12-28 20:20:24 +00:00
b9feac398f
* TargetData is no longer directly accessable from TM
...
* s/unsigned int/unsigned/
llvm-svn: 5175
2002-12-28 20:19:44 +00:00
a41b89a829
* TargetData is no longer directly accessable from TargetMachine
...
* Constpool & frame info is no longer directly in MachineFunction
llvm-svn: 5174
2002-12-28 20:18:21 +00:00
525e3af36c
* Frame & const pool info is no longer directly in MachineFunction
...
llvm-svn: 5173
2002-12-28 20:17:43 +00:00
d2a67df791
* Changes to be a MachineFunctionPass
...
* Frame information is now stuck in MachineFunctionInfo instead of directly
in MachineFunction.
* Don't require a TM as an argument to the ctor
llvm-svn: 5172
2002-12-28 20:16:08 +00:00
4d84d49f75
* Don't access TargetData directly
...
* Changes because frame info is not in MachineFunction directly anymore
llvm-svn: 5171
2002-12-28 20:15:01 +00:00
ccc2c7e8a7
Sparc is not little endian
...
llvm-svn: 5129
2002-12-24 00:02:38 +00:00
c6d6d62c8e
Initialize implicit uses/defs fields for sparc backend to empty list
...
llvm-svn: 4876
2002-12-03 05:41:54 +00:00
5961102d31
Fix misleading indentation
...
llvm-svn: 4730
2002-11-17 22:57:23 +00:00
a281003e5e
Remove a nasty little semi-colon someone introduced which
...
prevented any machine instrs from being printed!
llvm-svn: 4557
2002-11-06 00:34:26 +00:00
8cdd50d177
Reassociate pass now works
...
llvm-svn: 4473
2002-10-31 17:16:18 +00:00
9f205ddfdd
In getID(), don't call getValidSymbolName to mangle external names!
...
llvm-svn: 4451
2002-10-30 20:16:38 +00:00
c1d7563566
Sparc backend doesn't use target specific flags yet
...
llvm-svn: 4440
2002-10-30 01:07:12 +00:00
e2ac271173
These are no longer virtual methods
...
llvm-svn: 4420
2002-10-29 22:01:44 +00:00
b848956370
* Privatize the TargetName
...
* Move optSizeForSubWordData to TargetData
* Remove unused fields
llvm-svn: 4417
2002-10-29 21:48:17 +00:00
5667f0eefd
Allow TargetMachine to refuse static code gen
...
llvm-svn: 4415
2002-10-29 21:12:46 +00:00
69127c68ed
Remove unneccesary #includes
...
llvm-svn: 4408
2002-10-29 20:47:46 +00:00
71b6d491db
Rename Sparc.h to TargetMachineImpls.h
...
llvm-svn: 4407
2002-10-29 20:47:26 +00:00
ea0d174f1a
Bug fix: align size for dynamic allocas according to stack pointer
...
alignment restrictions. This is incomplete for one case.
llvm-svn: 4397
2002-10-29 19:37:31 +00:00
52ce69b8e2
*** empty log message ***
...
llvm-svn: 4390
2002-10-29 17:35:41 +00:00
01efae0bbf
MachineInstrInfo doesn't need a TargetMachine
...
llvm-svn: 4372
2002-10-29 15:45:20 +00:00
cbe6385890
Use BuildMI instead of explicit code.
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llvm-svn: 4362
2002-10-28 21:43:57 +00:00
5c7d638208
Remove all traces of the "Opcode Mask" field in the MachineInstr class
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llvm-svn: 4359
2002-10-28 21:17:20 +00:00
3d736950ea
Fix minor bug
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llvm-svn: 4355
2002-10-28 20:11:17 +00:00
9bebf832c8
Don't pass default args
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llvm-svn: 4354
2002-10-28 20:10:56 +00:00
181ea4a265
Rewrote uses of deprecated `MachineFunction::get(BasicBlock *BB)'.
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llvm-svn: 4352
2002-10-28 20:01:13 +00:00
6be5e92526
Replaced uses of deprecated `MachineFunction::get(BasicBlock *BB)'.
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llvm-svn: 4351
2002-10-28 20:00:31 +00:00
780090bbf1
Don't bother passing in default value
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llvm-svn: 4347
2002-10-28 19:46:25 +00:00
e3aa50d6b7
Fixes to work with updated RegAlloc
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llvm-svn: 4345
2002-10-28 19:32:07 +00:00
6a30b02b1d
Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()
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llvm-svn: 4331
2002-10-28 04:45:29 +00:00
2a3bd1c562
*** empty log message ***
...
llvm-svn: 4323
2002-10-28 02:01:37 +00:00
8710aab04c
Rename MachineCodeForBasicBlock to MachineBasicBlock
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llvm-svn: 4318
2002-10-28 01:41:47 +00:00
6d8a6c645c
Move machine code generation/destruction passes out of Sparc.cpp because
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they are generic
llvm-svn: 4310
2002-10-28 01:12:41 +00:00
e94db67c4f
Move addPassesToEmitAssembly from TargetMachine to UltraSparc because it
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really is sparc specific.
llvm-svn: 4308
2002-10-28 01:03:43 +00:00
7ae7f84cf3
Changed `MachineCodeForMethod' to `MachineFunction'.
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llvm-svn: 4301
2002-10-28 00:28:31 +00:00
fb34004733
change ++ to +1 when using random access iterators
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llvm-svn: 4292
2002-10-27 19:09:51 +00:00
d6786b5f59
Prune #includes
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llvm-svn: 4277
2002-10-25 02:01:33 +00:00
1e5e3f071e
Fix misspelling
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llvm-svn: 4276
2002-10-25 01:43:26 +00:00
42c66c4887
Minor cleanups
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Make sure to have a pass name
llvm-svn: 4268
2002-10-23 01:12:01 +00:00
ce64eddb71
- Two minor improvements to the MachineInstr class to reduce footprint and
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overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
bitvector. Sped up LLC a little less than 10% in a debug build!
llvm-svn: 4261
2002-10-22 23:16:21 +00:00
aaf6ee80de
Make sure to escape \'s when they are output
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llvm-svn: 4179
2002-10-15 19:56:24 +00:00
92ccbb9f27
Print "circular" warning message only in debug mode.
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llvm-svn: 4170
2002-10-14 16:32:49 +00:00
4049a9a5de
Removed misleading const keyword.
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llvm-svn: 4169
2002-10-14 16:32:24 +00:00
74cb2d2503
Allow emission of names that start with an underscore. This is needed to
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interface with code that uses symbols in the ansi-c protected namespace. In
most cases this comes from system header files, such as stdio.h. In particular,
without this change, a reference to the __iob symbol is mangled into ll_iob,
which is not resolved by libc.
llvm-svn: 4165
2002-10-14 06:14:18 +00:00
69ce8674b5
- Rename Instruction::First*Op to *OpsBegin, and Num*Ops to *OpsEnd to
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reflect the fact that it's a range being defined.
llvm-svn: 4147
2002-10-13 19:39:16 +00:00
10d8164013
Several major fixes, particularly in emitting constant aggregates:
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(1) Padding bytes between structure fields (for alignment) were never
being emitted into the constant pool so the layout did not match!
(2) In printing constants, structures containing structures or arrays
were never handled.
(3) Support new model for external/uninitialized/initialized globals.
Uninitialized globals are no longer emitted since they are external.
Initialized globals may go either in .bss or in .data.
llvm-svn: 4134
2002-10-13 00:32:18 +00:00
78044fbc8e
Don't use %l0 for large operands to a SAVE since it is needed *before* SAVE!
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We now use %g1 instead since that is shared and volatile.
llvm-svn: 4133
2002-10-13 00:24:06 +00:00
f4f7292b4e
Don't mark JMPLCALL and JMPLRET as branches.
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llvm-svn: 4132
2002-10-13 00:22:32 +00:00
d2dc60e5d9
(1) Try to evaluate constant when multiplying 2 constants.
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(2) Use intelligent multiply selection code for array allocas.
(3) Don't use cache padding for alloca'd stack slots!
(4) Bug fix in handling call arguments: was not copying sixth FP arg
to int reg. when calling a function with no prototype.
llvm-svn: 4130
2002-10-13 00:18:57 +00:00
Brian Gaeke