4 Commits

Author	SHA1	Message	Date
Ana Pazos	e3d248361e	[RISCV] Pass MCSubtargetInfo to print methods. ... Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345	2018-01-12 02:27:00 +00:00
Alex Bradbury	0d6cf90663	[RISCV] MC layer support for the standard RV32F instruction set extension ... The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020	2017-12-07 10:26:05 +00:00
Alex Bradbury	6758ecb98c	[RISCV] Add support for all RV32I instructions ... This patch supports all RV32I instructions as described in the RISC-V manual. A future patch will add support for pseudoinstructions and other instruction expansions (e.g. 0-arg fence -> fence iorw, iorw). Differential Revision: https://reviews.llvm.org/D23566 llvm-svn: 313485	2017-09-17 14:27:35 +00:00
Alex Bradbury	2fee9ead7e	[RISCV] Add RISCVInstPrinter and basic MC assembler tests ... With the addition of RISCVInstPrinter, it is now possible to test the basic operation of the RISCV MC layer. Differential Revision: https://reviews.llvm.org/D23564 llvm-svn: 310917	2017-08-15 13:08:29 +00:00