Commit Graph

930 Commits

Author SHA1 Message Date
Evan Cheng 9f3058f3be Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
llvm-svn: 58949
2008-11-10 01:08:07 +00:00
Anton Korobeynikov 9833d8c369 Temporary revert my last commit: it seems it's triggering some subtle bug in backend
and breaks llvm-gcc

llvm-svn: 58926
2008-11-08 23:05:05 +00:00
Anton Korobeynikov 09f51d1fd4 Factor out offset printing code into generic AsmPrinter.
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?

llvm-svn: 58917
2008-11-08 17:21:38 +00:00
Evan Cheng 436bdcdcca Moved InvalidateInstructionCache to ARMJITInfo::emitFunctionStub which knows size of stub.
llvm-svn: 58899
2008-11-08 08:16:49 +00:00
Evan Cheng b31a717527 Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
llvm-svn: 58897
2008-11-08 08:02:53 +00:00
Evan Cheng 98161f5f34 Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
llvm-svn: 58896
2008-11-08 07:38:22 +00:00
Evan Cheng bb373c4637 Fix relocation for calls to external symbols.
llvm-svn: 58893
2008-11-08 07:22:33 +00:00
Evan Cheng 077c8f8832 Skip over two-address use operands.
llvm-svn: 58883
2008-11-08 01:44:13 +00:00
Evan Cheng ffdd91e3b8 Handle ARM machine constantpool entry with non-lazy ptr.
llvm-svn: 58882
2008-11-08 01:31:27 +00:00
Evan Cheng 454ff53d58 Use ARMFunctionInfo to track number of constpool entries and jumptables.
llvm-svn: 58877
2008-11-08 00:51:41 +00:00
Evan Cheng ef4d78ba67 More code clean up.
llvm-svn: 58872
2008-11-07 22:57:53 +00:00
Evan Cheng 8467e2459a Get PIC jump table working.
llvm-svn: 58869
2008-11-07 22:30:53 +00:00
Dan Gohman cb0df597e0 Flush the raw_ostream after emitting the assembly for a function.
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.

llvm-svn: 58859
2008-11-07 19:49:17 +00:00
Evan Cheng 7095cd2af2 Jump table JIT support. Work in progress.
llvm-svn: 58836
2008-11-07 09:06:08 +00:00
Evan Cheng 98dc53e926 Encode misc arithmetic instructions.
llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng 49d665218c Encode extend instructions; more clean up.
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng 36ae40342f Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng b870fd8874 Fix so_imm encoding bug; add support for MOVi2pieces.
llvm-svn: 58790
2008-11-06 02:25:39 +00:00
Evan Cheng 2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs.
llvm-svn: 58780
2008-11-05 23:22:34 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Dan Gohman f14b77ebf1 Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
2008-11-05 04:14:16 +00:00
Evan Cheng e3827d9061 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
llvm-svn: 58725
2008-11-04 22:19:55 +00:00
Evan Cheng 297b32a367 Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
llvm-svn: 58714
2008-11-04 19:57:48 +00:00
Evan Cheng 4eaff40147 Debug output tweak.
llvm-svn: 58708
2008-11-04 17:58:53 +00:00
Evan Cheng 453844c352 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
llvm-svn: 58707
2008-11-04 17:57:07 +00:00
Evan Cheng 9340be4641 For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688
2008-11-04 09:30:48 +00:00
Evan Cheng 2299c99d79 Stylistic change.
llvm-svn: 58683
2008-11-04 06:10:06 +00:00
Evan Cheng 6dd08b6604 Handle ARM machine constantpool entries.
llvm-svn: 58671
2008-11-04 00:50:32 +00:00
Evan Cheng f60e5aaaac Remove a dead switch statement.
llvm-svn: 58644
2008-11-03 21:26:52 +00:00
Evan Cheng 3620e685b5 Minor code restructuring. No functionality change.
llvm-svn: 58643
2008-11-03 21:02:39 +00:00
Jim Grosbach 4d0549e3be Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Dan Gohman ac41d9f5d8 Refactor various TargetAsmInfo subclasses' TargetMachine members away
adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624
2008-11-03 18:22:42 +00:00
Evan Cheng 83bf3de134 Add comment.
llvm-svn: 58533
2008-10-31 19:56:03 +00:00
Evan Cheng 20dbb3bcad Use better data structure for ConstPoolId2AddrMap.
llvm-svn: 58532
2008-10-31 19:55:13 +00:00
Evan Cheng 44994e0c77 Actually make debug output understandable.
llvm-svn: 58529
2008-10-31 19:15:52 +00:00
Evan Cheng 8fce66a47c Forgot this in last commit.
llvm-svn: 58527
2008-10-31 19:11:09 +00:00
Evan Cheng 467e6e8093 Encode PICADD; some code clean up.
llvm-svn: 58526
2008-10-31 19:10:44 +00:00
Evan Cheng c696ef9b11 I think we got non-machine specific constpool entries covered.
llvm-svn: 58474
2008-10-30 23:43:36 +00:00
Evan Cheng 66cff408ff ARM JIT should observe -relocation-model command line option.
llvm-svn: 58433
2008-10-30 16:10:54 +00:00
Evan Cheng 19d64ba8bf Correct way to handle CONSTPOOL_ENTRY instructions.
llvm-svn: 58409
2008-10-29 23:55:43 +00:00
Evan Cheng de9dbc5584 Add debugging support.
llvm-svn: 58408
2008-10-29 23:55:17 +00:00
Jim Grosbach ff2b4948ce Support for constant islands in the ARM JIT.
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338
2008-10-28 18:25:49 +00:00
David Greene ce2a938186 Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278
2008-10-27 21:56:29 +00:00
Oscar Fuentes 9ba4650b76 CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.
llvm-svn: 58133
2008-10-25 03:40:32 +00:00
Jim Grosbach 1ecf1fd5c8 remove extraneous #ifdef's
llvm-svn: 58006
2008-10-22 22:27:51 +00:00
Oscar Fuentes f3c03b02dc CMake: Turned some libraries into partially linked objects. Corrected
names of LLVMCore and ARMCodeGen.

llvm-svn: 57943
2008-10-22 02:51:53 +00:00
Jim Grosbach cfebc18d7c use pre-UAL mnemonics for push/pop for compilaton callback function
llvm-svn: 57911
2008-10-21 16:54:12 +00:00
Jim Grosbach 9396051e3d Update the stub and callback code to handle lazy compilation. The stub
is re-written by the callback to branch directly to the compiled code
in future invocations.

Added back in range-based memory permission functions for the updating of
the stub on Darwin.

llvm-svn: 57846
2008-10-20 21:39:23 +00:00
Dan Gohman 33332bce17 Const-ify several TargetInstrInfo methods.
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
Evan Cheng 07d53b1d33 Rename LoadX to LoadExt.
llvm-svn: 57526
2008-10-14 21:26:46 +00:00
Jim Grosbach b7c01f5f48 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
llvm-svn: 57524
2008-10-14 20:36:24 +00:00
Dan Gohman 9c4b7d5c4f Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521
2008-10-14 20:25:08 +00:00
Chris Lattner 2753955fc0 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
2008-10-11 22:08:30 +00:00
Jim Grosbach d83529e8c4 Comment to be explicit that the enumeration values for CondCodes matter.
llvm-svn: 57295
2008-10-08 16:24:35 +00:00
Jim Grosbach f311fe142c Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
llvm-svn: 57262
2008-10-07 21:08:09 +00:00
Jim Grosbach b53acd8caa need ARM.h for ARMCC definition
llvm-svn: 57261
2008-10-07 21:01:51 +00:00
Jim Grosbach c084e84028 Encode the conditional execution predicate when JITing.
llvm-svn: 57258
2008-10-07 19:05:35 +00:00
Jim Grosbach 2fb5c3938b Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
llvm-svn: 57252
2008-10-07 17:42:09 +00:00
Jim Grosbach 1d54d4f375 Fix Opcode values of CMP and CMN
llvm-svn: 57251
2008-10-07 17:40:46 +00:00
Anton Korobeynikov d2aded08ac Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
llvm-svn: 57106
2008-10-05 08:53:29 +00:00
Dan Gohman 2c836cf187 Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016
2008-10-03 16:55:19 +00:00
Jim Grosbach 332ad5e016 Indexing off by one resulted in errant encoding of source register for
reg->reg moves.

llvm-svn: 57011
2008-10-03 15:53:56 +00:00
Jim Grosbach af929abc01 NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub
for global relocations that do need them (libc calls, for example).

llvm-svn: 57010
2008-10-03 15:52:42 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Jim Grosbach 3dc0a3bce3 Fix typo s/ther/there/
llvm-svn: 56924
2008-10-01 18:16:49 +00:00
Duncan Sands 08d91178e9 Rename isWeakForLinker to mayBeOverridden. Use it
instead of hasWeakLinkage in a bunch of optimization
passes.

llvm-svn: 56782
2008-09-29 11:25:42 +00:00
Evan Cheng 3774b2f292 Re-apply 56683 with fixes.
llvm-svn: 56748
2008-09-27 01:56:22 +00:00
Bill Wendling c966a737c5 Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include  -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...

llvm-svn: 56703
2008-09-26 22:10:44 +00:00
Evan Cheng d77cbe8947 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
Dale Johannesen 0e32a2c935 Add "inreg" field to CallSDNode (doesn't increase
its size).  Adjust various lowering functions to
pass this info through from CallInst.  Use it to
implement sseregparm returns on X86.  Remove
X86_ssecall calling convention.

llvm-svn: 56677
2008-09-26 19:31:26 +00:00
Oscar Fuentes cdc95498f5 CMake: Builds all targets.
llvm-svn: 56641
2008-09-26 04:40:32 +00:00
Anton Korobeynikov 87001fd6fd Reapply 56585:56589 with proper fix for some gcc versions
llvm-svn: 56621
2008-09-25 21:00:33 +00:00
Evan Cheng 84301390ae Temporarily backing out 56585:56589 to unbreak the build.
llvm-svn: 56607
2008-09-25 07:38:08 +00:00
Anton Korobeynikov a9163feefe Get rid of virtual inheritance for ARM TAI
llvm-svn: 56587
2008-09-24 22:22:27 +00:00
Anton Korobeynikov 8e7b93938d Get rid of ReadOnlySection duplicate
llvm-svn: 56582
2008-09-24 22:20:27 +00:00
Anton Korobeynikov 5906234c1d Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
llvm-svn: 56580
2008-09-24 22:18:54 +00:00
Anton Korobeynikov 22db30548d Get rid of duplicate char*/Section* stuff for TLS sections
llvm-svn: 56577
2008-09-24 22:17:06 +00:00
Anton Korobeynikov 7497762606 Get rid of duplicate char*/Section* DataSection
llvm-svn: 56575
2008-09-24 22:16:16 +00:00
Anton Korobeynikov 076e905b94 Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
llvm-svn: 56573
2008-09-24 22:14:23 +00:00
Anton Korobeynikov 69ff51baa0 Drop obsolete hook and change all usage to new interface
llvm-svn: 56572
2008-09-24 22:13:07 +00:00
Dan Gohman ed1cf1a8f1 Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.

llvm-svn: 56497
2008-09-23 18:42:32 +00:00
Dale Johannesen 7a74e71489 Make log, log2, log10, exp, exp2 use Expand by
default.

llvm-svn: 56471
2008-09-22 21:57:32 +00:00
Evan Cheng 933b392f65 Duh. Default to ARMCC::AL (always).
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
Evan Cheng 5e3ac187d9 Clean up.
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
Evan Cheng bc0d0eccf3 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Evan Cheng 7848cfcd77 Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng 937569afe3 Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Bill Wendling 24c79f28b1 Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Bill Wendling 8bc392fb1d - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Evan Cheng a5804effed Fix random abort.
llvm-svn: 56184
2008-09-13 01:55:59 +00:00
Dan Gohman d3fe174c53 Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
2008-09-13 01:54:27 +00:00
Evan Cheng 380482ac46 Typo.
llvm-svn: 56182
2008-09-13 01:44:01 +00:00
Evan Cheng ba28161103 Rely on instruction format to determine so_reg operand for now.
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng db6571a2c7 Accidentially flipped the condition.
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
Evan Cheng 25a39094f8 Add debug dumps.
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng d1424c4eca Addrmode 1 S bit can be dynamically set. Look for CPSR def.
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
Evan Cheng 33fa89c6fb Rewrite address mode 1 code emission routines.
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Jim Grosbach a7cd7bc353 udpate header comment: s/VP/VFP/
llvm-svn: 56126
2008-09-11 21:41:29 +00:00
Dale Johannesen f080225490 Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton).  Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).

llvm-svn: 55973
2008-09-09 01:21:22 +00:00
Dan Gohman 4d5b5fe812 Delete an unused variable.
llvm-svn: 55915
2008-09-08 16:28:17 +00:00
Dan Gohman a79db30d28 Tidy up several unbeseeming casts from pointer to intptr_t.
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
Dale Johannesen da2d80688b Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).

llvm-svn: 55753
2008-09-04 00:47:13 +00:00
Evan Cheng df8cdc3717 Add Mac OS X compatible JIT callback routine.
llvm-svn: 55625
2008-09-02 07:49:03 +00:00
Evan Cheng 3be5b728b1 Revamp ARM JIT.
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
Evan Cheng fa558788e7 Control flow instruction encodings.
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng c288cc0572 ldm / stm instruction encodings.
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng c37532b24a AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng a282723499 Reorganize instruction formats again; AXI1 encoding.
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng 169eccc24e addrmode3 instruction encodings.
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng 624844b4dd Reorganize some instruction format definitions. No functionality change.
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng cccca875b1 Rest of addrmode2 instruction encodings.
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng 01fd3f129a Addr2 word / byte load encodings.
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng 5b6c931e1f Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Evan Cheng 44b2138b9a TableGen'ing instruction encodings.
llvm-svn: 55533
2008-08-29 07:42:03 +00:00
Evan Cheng c139c221dd addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
llvm-svn: 55531
2008-08-29 07:40:52 +00:00
Evan Cheng 9f717afd68 MVN is addrmode1.
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng ee98fa9db2 More refactoring.
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Evan Cheng 2d37f19ef2 Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Gabor Greif f304a7aa4d erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Gabor Greif abfdf928d8 disallow direct access to SDValue::ResNo, provide a getter instead
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Owen Anderson 27fb3dcbc7 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Chris Lattner 0c19df4871 Switch the asmprinter (.ll) and all the stuff it requires over to
use raw_ostream instead of std::ostream.  Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).

Other interesting changes:
 1) This makes Value::print be non-virtual.
 2) AP[S]Int and ConstantRange can no longer print to ostream directly, 
    use raw_ostream instead.
 3) This fixes a bug in raw_os_ostream where it didn't flush itself 
    when destroyed.
 4) This adds a new SDNode::print method, instead of only allowing "dump".


A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream 
versions.

This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.

llvm-svn: 55263
2008-08-23 22:23:09 +00:00
Dan Gohman eb0cee91f6 Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Dan Gohman d3582c9bda Simplify SelectRoot's interface, and factor out some common code
from all targets.

llvm-svn: 55124
2008-08-21 16:36:34 +00:00
Owen Anderson 9371964f47 Use raw_ostream throughout the AsmPrinter.
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
Evan Cheng 0d19699e52 ARM asm printer can't handle dwarf info yet.
llvm-svn: 54913
2008-08-18 08:52:48 +00:00
Anton Korobeynikov 17d28de8ac Move ARM to pluggable asmprinter
llvm-svn: 54889
2008-08-17 13:55:10 +00:00
Owen Anderson 4f6bf04616 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Jim Grosbach 643e60e19c Whitespace cleanup. Test commit.
llvm-svn: 54695
2008-08-12 18:34:45 +00:00
Anton Korobeynikov ed47329174 Handle visibility printing with all generality. Remove bunch of duplicate code.
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
Evan Cheng df8c7faf60 Undo most of r54519.
llvm-svn: 54534
2008-08-08 17:56:50 +00:00
Evan Cheng 655fa0fec4 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
Anton Korobeynikov 04083529df Switch ARM to new section handling stuff
llvm-svn: 54458
2008-08-07 09:54:23 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng c90a11256e Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
llvm-svn: 54004
2008-07-25 00:55:17 +00:00
Dan Gohman 1705968102 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Chris Lattner 9fc580f2d0 add support for returning i128, PR2532.
llvm-svn: 53472
2008-07-11 20:53:00 +00:00
Dan Gohman 0597e5b697 Trim unnecessary #includes.
llvm-svn: 53471
2008-07-11 20:38:31 +00:00
Dale Johannesen c4650f4b56 Emit debug info for data-only files. ARM version.
llvm-svn: 53360
2008-07-09 21:20:54 +00:00
Evan Cheng 49c8e68e4c Back out 53254. It broke ppc debug info codegen.
llvm-svn: 53280
2008-07-09 06:36:53 +00:00
Dale Johannesen b9097a71d4 Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254
2008-07-08 21:56:22 +00:00
Dan Gohman 3b46030375 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Dan Gohman c7fc432b19 Minor const-correctness fixes.
llvm-svn: 53196
2008-07-07 20:06:06 +00:00