2cb9068c78
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
...
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
5420516b3f
This method should be virtual
...
llvm-svn: 46723
2008-02-04 23:04:24 +00:00
ef14d5f926
Eliminate some redundant code.
...
llvm-svn: 46720
2008-02-04 21:44:06 +00:00
1770fb883b
explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
...
llvm-svn: 46676
2008-02-03 05:43:57 +00:00
e99faac423
don't do ReplaceUses on a result that doesn't exist.
...
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
32e5347eb8
Get rid of the annoying blank lines before labels.
...
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
efd142a920
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
llvm-svn: 46659
2008-02-02 04:07:54 +00:00
27b32b87ed
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
...
llvm-svn: 46623
2008-01-31 21:00:00 +00:00
3646fdda67
Create a new class, MemOperand, for describing memory references
...
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
llvm-svn: 46585
2008-01-31 00:25:39 +00:00
29cfb67e28
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
...
instruction at the end.
llvm-svn: 46562
2008-01-30 18:18:23 +00:00
47a7d6fafe
Factor the addressing mode and the load/store VT out of LoadSDNode
...
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
llvm-svn: 46538
2008-01-30 00:15:11 +00:00
96a1b810ec
If the function has no machine instructions, then emit a "nop" so that
...
the function label isn't associated with something it shouldn't be.
llvm-svn: 46449
2008-01-28 09:15:03 +00:00
95d46ef887
The last pieces needed for loading arbitrary
...
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
llvm-svn: 46280
2008-01-23 20:39:46 +00:00
7f1ff5fedd
Honor explicit section information on Darwin.
...
llvm-svn: 46267
2008-01-23 00:58:14 +00:00
8ef89eabc2
Revert the part of 45849 that treated weak globals
...
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
llvm-svn: 46147
2008-01-17 23:36:04 +00:00
1ea55cf816
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
9a249b0ce5
rename SDTRet -> SDTNone.
...
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
llvm-svn: 46017
2008-01-15 22:02:54 +00:00
1ba66e0cec
Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead.
...
llvm-svn: 46016
2008-01-15 22:02:46 +00:00
596875118c
rename MachineInstr::setInstrDescriptor -> setDesc
...
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
193daf0698
Weak zeroes don't go in bss on Darwin.
...
llvm-svn: 45849
2008-01-11 01:59:45 +00:00
94de7bc3aa
get def use info more correct.
...
llvm-svn: 45821
2008-01-10 05:12:37 +00:00
7250120177
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
...
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
03ad885039
rename TargetInstrDescriptor -> TargetInstrDesc.
...
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
e99a6caee4
Rename all the M_* flags to be namespace qualified enums, and switch
...
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
llvm-svn: 45692
2008-01-07 06:42:05 +00:00
b0d06b4381
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
...
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
f0f438a517
remove MachineOpCode typedef.
...
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
a98c679de0
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
...
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
2008-01-07 01:56:04 +00:00
2a3be7bb6c
Move even more functionality from MRegisterInfo into TargetInstrInfo.
...
Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
...
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
10324d0175
rename isStore -> mayStore to more accurately reflect what it captures.
...
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
f4d55ec4e8
remove explicit isStore flags that are now inferrable.
...
llvm-svn: 45653
2008-01-06 05:55:01 +00:00
6bb0c52628
Move some more functionality from MRegisterInfo to TargetInstrInfo.
...
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
eee14601b1
Move some more instruction creation methods from RegisterInfo into InstrInfo.
...
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
25568e4cef
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
...
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
7a73ae9a86
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
...
Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
a10fff51d9
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
...
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
llvm-svn: 45467
2007-12-31 04:13:23 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
...
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
...
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
b3fd2d7b63
use simplified operand addition methods.
...
llvm-svn: 45437
2007-12-30 01:01:54 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
a087a8d2ce
remove attribution from lib Makefiles.
...
llvm-svn: 45415
2007-12-29 20:09:26 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
...
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
92105ac0cd
Doh
...
llvm-svn: 44694
2007-12-08 01:01:07 +00:00
cd6913627e
Fix a compilation warning.
...
llvm-svn: 44692
2007-12-08 01:00:31 +00:00
bb26301864
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
...
the stored register is killed.
llvm-svn: 44600
2007-12-05 03:14:33 +00:00
f45a1d623c
Remove redundant foldMemoryOperand variants and other code clean up.
...
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
69fda0a716
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
...
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
57662f3882
several entries got significantly better, though they still aren't done.
...
llvm-svn: 44382
2007-11-27 22:41:52 +00:00
f3f4ad9dd6
implement a trivial readme entry.
...
llvm-svn: 44380
2007-11-27 22:36:16 +00:00
f81d5886c6
Several changes:
...
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
llvm-svn: 44300
2007-11-24 07:07:01 +00:00
7a7085f6d3
Add parameter to getDwarfRegNum to permit targets
...
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
llvm-svn: 44056
2007-11-13 19:13:01 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
...
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
...
Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
...
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
797d56ff17
Much improved pic jumptable codegen:
...
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 01:32:10 +00:00
f6a67bf700
[ARM] Implement __builtin_thread_pointer.
...
llvm-svn: 43892
2007-11-08 17:20:05 +00:00
fa0df55bdd
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
...
Thanks for the suggestions Bill :-)
llvm-svn: 43742
2007-11-05 23:12:20 +00:00
1a30c18e88
[ARM] Fix code generation for:
...
static __thread struct {
int a;
int b;
} teste = {0, 0};
llvm-svn: 43722
2007-11-05 18:33:37 +00:00
283207a71c
Eliminate the remaining uses of getTypeSize. This
...
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
llvm-svn: 43688
2007-11-05 00:04:43 +00:00
419b6d7ce4
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
...
and by restructuring the X86 version.
New I just have to move this to a common place :-)
llvm-svn: 43554
2007-10-31 14:39:58 +00:00
063f177300
Make ARM an X86 memcpy expansion more similar to each other.
...
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
llvm-svn: 43552
2007-10-31 11:52:06 +00:00
65e804a9c3
Support non-POSIX hosts by removing use of strncasecmp.
...
llvm-svn: 43364
2007-10-25 21:54:43 +00:00
1f2dd35898
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
...
llvm-svn: 43234
2007-10-22 22:11:27 +00:00
18a831d783
split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
...
llvm-svn: 43176
2007-10-19 14:35:17 +00:00
5d979d57ae
Add an easy microoptimization I noticed.
...
llvm-svn: 43164
2007-10-19 03:29:26 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
...
- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
...
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
79dfbed6f6
Fix a misnamed parameter.
...
llvm-svn: 43145
2007-10-18 19:29:45 +00:00
84f3461c49
legalizing the ret operation on f64 shouldn't introduce a new
...
i64 bit convert needlessly.
llvm-svn: 43116
2007-10-18 06:17:07 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
482732af9d
Set ISD::FPOW to Expand.
...
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
f4cf5dcdd2
- Added a few target hooks to generate load / store instructions from / to any
...
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
llvm-svn: 42621
2007-10-05 01:32:41 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
0b7cf862bc
AsmPrinters overriding getAnalysisUsage should call super.
...
And not super's super, either.
llvm-svn: 42482
2007-09-30 13:39:29 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
57211c5550
More explicit keywords.
...
llvm-svn: 42316
2007-09-25 20:27:06 +00:00
1ff71872c2
Honor user-defined section specification of a global, ignores whether its initializer is null.
...
llvm-svn: 42182
2007-09-21 00:41:19 +00:00
8010320365
Enable if-conversion for ARM by default.
...
llvm-svn: 42156
2007-09-20 00:48:22 +00:00
d0e360e16e
Avoid referencing deleted instruction.
...
llvm-svn: 42153
2007-09-19 21:48:07 +00:00
9da02f5ee2
Remove isReg, isImm, and isMBB, and change all their users to use
...
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
66c22e8fd6
Enable indirect encoding for the personality function
...
llvm-svn: 41873
2007-09-11 23:55:40 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
...
init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
f948772f9e
80 col.
...
llvm-svn: 41812
2007-09-10 22:22:23 +00:00
6777b72659
Add some notes about better flag handling.
...
llvm-svn: 41808
2007-09-10 21:43:18 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
...
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
ab871baaf8
Instruction formats added used to generate multiply instructions of V5TE.
...
llvm-svn: 41629
2007-08-30 23:34:14 +00:00
ff32b62942
Unused relocation type reloc_arm_absolute removed.
...
llvm-svn: 41628
2007-08-30 23:31:35 +00:00
1457b2b3b1
Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
...
llvm-svn: 41627
2007-08-30 23:29:26 +00:00
73489273ae
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
...
llvm-svn: 41626
2007-08-30 23:25:47 +00:00
ae1b924c79
JITInfo now resolves function addrs and also relocations. It always emits a stub.
...
llvm-svn: 41625
2007-08-30 23:21:27 +00:00
9a25d98c86
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
...
llvm-svn: 41597
2007-08-30 05:52:20 +00:00
f7c6effc44
Initial JIT support for ARM by Raul Fernandes Herbster.
...
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
5f6a9da530
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
aa39b39eec
Indexed loads each has 2 outputs.
...
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
e379f08b19
More explicit keywords.
...
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
...
still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
...
AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
ac1591be42
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
...
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
22b0c344db
Only adjust esp around calls in presence of alloca.
...
llvm-svn: 40030
2007-07-19 00:42:58 +00:00
396156e00b
no email addrs in file headers
...
llvm-svn: 39962
2007-07-17 05:56:43 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
85ee72f7ba
ARM: make branch folder remove unconditional branches
...
following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
llvm-svn: 39782
2007-07-12 16:45:35 +00:00
e59411d056
Fix hang compiling TimberWolf (allow for islands
...
of size other than 4).
llvm-svn: 39743
2007-07-11 18:32:38 +00:00
94579dbd2e
Didn't mean the last commit. Revert.
...
llvm-svn: 38515
2007-07-10 22:00:16 +00:00
effa7467b6
Update.
...
llvm-svn: 38513
2007-07-10 21:49:47 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
...
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
...
zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
881248c4e1
No need for ccop anymore.
...
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
3650b2c278
Incorrect check.
...
llvm-svn: 37962
2007-07-06 23:23:19 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
...
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
0a42fdf346
Print the s bit if the instruction is toggled to its CPSR setting form.
...
llvm-svn: 37932
2007-07-06 01:01:34 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
...
llvm-svn: 37931
2007-07-06 01:00:49 +00:00
9546a5c7de
Initial ARM JIT support by Raul Fernandes Herbster.
...
llvm-svn: 37926
2007-07-05 21:15:40 +00:00
085314b455
Unbreak the build.
...
llvm-svn: 37914
2007-07-05 17:13:19 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
...
Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
94f04c6fc9
Reflects the chanegs made to PredicateOperand.
...
llvm-svn: 37898
2007-07-05 07:18:20 +00:00
a7f77599a4
Added ARM::CPSR to represent ARM CPSR status register.
...
llvm-svn: 37897
2007-07-05 07:17:13 +00:00
7e90b11550
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
...
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
...
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
49ffa1e488
Added ARM::CPSR to represent ARM CPSR status register.
...
llvm-svn: 37894
2007-07-05 07:11:03 +00:00
2660cef6d7
Convert .cvsignore files
...
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
335c65e9a4
Silence a warning.
...
llvm-svn: 37737
2007-06-26 18:31:22 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
0c550df9d2
Fix the build.
...
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
...
llvm-svn: 37700
2007-06-22 00:54:56 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
...
llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
...
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
36b1f5476e
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
...
llvm-svn: 37606
2007-06-15 21:15:00 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
c7ebbaa10e
Define AsmTransCBE for ARM.
...
llvm-svn: 37527
2007-06-08 21:06:23 +00:00
6740da9407
Fix ARM condition code subsumission check.
...
llvm-svn: 37517
2007-06-08 09:14:47 +00:00
f62a5afb98
tBcc is not a barrier.
...
llvm-svn: 37516
2007-06-08 09:13:23 +00:00
842be09d86
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
...
llvm-svn: 37484
2007-06-07 01:37:54 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
...
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
5c48958a61
Print predicate of the second instruction of the two-piece constant MI.
...
llvm-svn: 37437
2007-06-05 18:55:18 +00:00
252695f0f6
PIC label asm printing cosmetic changes.
...
llvm-svn: 37434
2007-06-05 07:36:38 +00:00
446548d2a3
update this entry, now that Anton implemented shift/and lowering for
...
switches. There is one really easy isel thing here with tst we are not
getting.
llvm-svn: 37400
2007-06-02 18:45:14 +00:00
9aa5fc8577
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
...
llvm-svn: 37388
2007-06-01 20:51:29 +00:00
256144de4a
Set ARM ifcvt duplication limit to 3 for now.
...
llvm-svn: 37385
2007-06-01 08:28:59 +00:00
a2ab4e5feb
Make jumptable non-predicable for now.
...
llvm-svn: 37381
2007-06-01 00:56:15 +00:00
3e3ff30aa2
Fix the asmprinter so that a globalvalue can specify an explicit alignment
...
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
llvm-svn: 37373
2007-05-31 18:57:45 +00:00
19eeee41ca
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
...
llvm-svn: 37351
2007-05-29 23:34:19 +00:00
a6e9a4ce07
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
...
llvm-svn: 37349
2007-05-29 23:32:06 +00:00
2d91a4fd6a
Add missing const qualifiers.
...
llvm-svn: 37342
2007-05-29 18:42:18 +00:00
1d764eca98
Hooks for predication support.
...
llvm-svn: 37308
2007-05-23 07:22:05 +00:00
8c8afb27d7
Fix some -march=thumb regressions. tBR_JTr is not predicable.
...
llvm-svn: 37272
2007-05-21 23:17:32 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
...
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
...
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
147b334b6a
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
...
llvm-svn: 37268
2007-05-21 18:56:31 +00:00
4ae1840d21
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
...
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
ea623560f8
Silence some compilation warnings.
...
llvm-svn: 37197
2007-05-18 01:19:57 +00:00
6addd65914
Set ARM if-conversion block size threshold to 10 instructions for now.
...
llvm-svn: 37194
2007-05-18 00:19:34 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
58698d2534
More effective breakdown of memcpy into repeated load/store. These are now
...
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
llvm-svn: 37179
2007-05-17 21:31:21 +00:00
1634e7186b
ARM::tB is also predicable.
...
llvm-svn: 37125
2007-05-16 21:53:43 +00:00
dcff2eb0e8
PredicateInstruction returns true if the operation was successful.
...
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
4423687831
Move if-conversion after all passes that may use register scavenger.
...
llvm-svn: 37120
2007-05-16 20:52:46 +00:00
e2762c3d68
Removed isPredicable().
...
llvm-svn: 37119
2007-05-16 20:50:23 +00:00
dcd6cdf896
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
...
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
01a4227ed1
Conditional branch is not a barrier.
...
llvm-svn: 37103
2007-05-16 07:45:54 +00:00
c95f95b6da
Fix comment.
...
llvm-svn: 37098
2007-05-16 05:14:06 +00:00
ad3aac71ce
Hooks for predication support.
...
llvm-svn: 37093
2007-05-16 02:01:49 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
...
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
1b8d46ab21
Fix previous patch. GOTOFF can be used only when the symbol has internal
...
linkage or hidden visibility.
llvm-svn: 37055
2007-05-14 23:20:21 +00:00
d705f5d51d
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
...
and used in the same module.
llvm-svn: 37044
2007-05-14 18:46:23 +00:00
3551928a2b
Enable aliases on arm-linux.
...
llvm-svn: 37042
2007-05-14 18:32:56 +00:00
9c031c0ddf
Switch BCC, MOVCCr, etc. to PredicateOperand.
...
llvm-svn: 36948
2007-05-08 21:08:43 +00:00
744350b131
Fix PR1390 in a better way.
...
llvm-svn: 36916
2007-05-07 23:15:16 +00:00
d37c23745f
This is no longer needed after enabling the DAG combiner xform.
...
llvm-svn: 36909
2007-05-07 21:29:41 +00:00
34b2735f20
Fix PR1390.
...
Don't spill extra register to align the stack.
llvm-svn: 36814
2007-05-05 23:44:41 +00:00
8f8199086f
Add a processor.
...
llvm-svn: 36765
2007-05-04 22:16:30 +00:00
33c9886001
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
...
llvm-svn: 36718
2007-05-04 00:26:58 +00:00
23040754b0
Should never see an indexed load / store with zero offset.
...
llvm-svn: 36714
2007-05-03 23:30:36 +00:00
89200ce0f0
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
...
llvm-svn: 36693
2007-05-03 20:54:42 +00:00
83930198dd
Debug support for arm-linux.
...
Patch by Raul Herbster.
llvm-svn: 36690
2007-05-03 20:28:35 +00:00
9a8c7cf00b
add support for printing offset from global
...
llvm-svn: 36669
2007-05-03 16:42:23 +00:00
bef131de68
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
...
llvm-svn: 36663
2007-05-03 02:00:18 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
1c1082133c
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
...
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
9ce17f1e33
Add some support for (Darwin) code-generating directives in getInlineAsmLength.
...
Support is incomplete, but more accurate than gcc's.
llvm-svn: 36634
2007-05-02 01:02:40 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
fa34bc9623
Doh. PC displacement is between the constantpool and the add instruction.
...
llvm-svn: 36630
2007-05-01 20:27:19 +00:00
5662b21db1
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
...
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
8dd36a51fc
Remove item: thumb padding in constant islands
...
llvm-svn: 36586
2007-04-30 00:32:06 +00:00
71577f3848
remove unused variable
...
llvm-svn: 36585
2007-04-30 00:30:48 +00:00
2c673ad7ef
Enable protected visibility on ARM.
...
llvm-svn: 36583
2007-04-30 00:23:51 +00:00
4a00cf3fc4
Rewrite of Thumb constant islands handling (exact allowance for padding
...
around islands and jump tables).
llvm-svn: 36573
2007-04-29 19:19:30 +00:00
1ee29dd026
Make ARM-specific version of getInlineAsmLength
...
llvm-svn: 36572
2007-04-29 19:17:45 +00:00
7e7280b538
change per review
...
llvm-svn: 36519
2007-04-28 00:36:37 +00:00
29c05756b5
Prevent Thumb code from generating ARM instructions
...
llvm-svn: 36518
2007-04-27 22:17:18 +00:00
99cb63029a
add parenthesis.
...
llvm-svn: 36514
2007-04-27 20:10:08 +00:00
559c546453
Doh. ARM::LEApcrel is a single instruction MI.
...
llvm-svn: 36513
2007-04-27 18:27:13 +00:00
62f65468bc
In Thumb mode, the frame register must be R7.
...
llvm-svn: 36512
2007-04-27 17:58:03 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
...
llvm-svn: 36506
2007-04-27 13:54:47 +00:00
c9f22fd1a4
Darwin runtime library does not have these.
...
llvm-svn: 36505
2007-04-27 08:15:43 +00:00
d9990f061f
Special handling of LEApcrel and tLEApcrel.
...
llvm-svn: 36504
2007-04-27 08:14:15 +00:00
e54018687d
Back out previous check-in. Incorrect.
...
llvm-svn: 36503
2007-04-27 07:50:02 +00:00
68ec63b3d7
tLEApcrel is a AddrModeTs, i.e. pc relative.
...
llvm-svn: 36502
2007-04-27 07:37:22 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
4ae9425bb6
remember to emit weak reference in one more case.
...
llvm-svn: 36438
2007-04-25 14:50:40 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
fdfb757682
Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
...
BBOffsets and BBSizes when adjusting conditional branches.
llvm-svn: 36372
2007-04-23 20:09:04 +00:00
ed0ecdb7ff
add Align field, and use when generating function alignment
...
llvm-svn: 36371
2007-04-23 20:07:25 +00:00
8eb9bff493
add isThumb (unused as yet)
...
llvm-svn: 36370
2007-04-23 20:04:35 +00:00
ee2d164f0f
Implement PIC for arm-linux.
...
llvm-svn: 36324
2007-04-22 00:04:12 +00:00
e656d093a5
Specify S registers as D registers' sub-registers.
...
llvm-svn: 36280
2007-04-20 21:20:10 +00:00
3d3f22766a
add a crazy idea
...
llvm-svn: 36273
2007-04-20 20:18:43 +00:00
42cd7253b1
Fix a bug in getFrameRegister.
...
Reported by Raul Herbster.
llvm-svn: 36262
2007-04-19 14:09:38 +00:00
598bc0d9a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
...
llvm-svn: 36222
2007-04-17 22:39:58 +00:00
2509d7547d
add a note
...
llvm-svn: 36203
2007-04-17 18:03:00 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
502c3f48d9
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
...
llvm-svn: 35962
2007-04-13 06:50:55 +00:00
fe926e2960
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
...
llvm-svn: 35909
2007-04-11 16:17:12 +00:00
9b6d69e0c2
restore support for negative strides
...
llvm-svn: 35859
2007-04-10 03:48:29 +00:00
d44e24c896
remove dead target hooks
...
llvm-svn: 35846
2007-04-09 23:33:39 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
1e150dedd1
Implement inline asm modifier P.
...
llvm-svn: 35640
2007-04-04 00:13:29 +00:00
bd31f41daa
Typo.
...
llvm-svn: 35639
2007-04-04 00:06:07 +00:00
3c68d4e8ba
Remove unused constant pool entries.
...
llvm-svn: 35635
2007-04-03 23:39:48 +00:00
39d8b4db92
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
...
llvm-svn: 35627
2007-04-03 21:31:21 +00:00
e8315fe3f5
Inverted logic.
...
llvm-svn: 35619
2007-04-03 06:44:25 +00:00
f742e2fe70
Arm supports negative strides as well, add them. This lets us compile:
...
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
llvm-svn: 35609
2007-04-03 00:13:57 +00:00
d13786dd82
fix off by 1 error in displacement computation
...
llvm-svn: 35602
2007-04-02 20:31:06 +00:00
8e168a4f36
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
...
to be folded into non-store instructions.
llvm-svn: 35601
2007-04-02 18:51:18 +00:00
6223e83f6d
add support for the 'w' inline asm register class.
...
llvm-svn: 35598
2007-04-02 17:24:08 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
...
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
17d48a8bc2
Add i16 address mode.
...
llvm-svn: 35551
2007-04-01 08:06:46 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
045414aa8e
New entry.
...
llvm-svn: 35480
2007-03-29 21:40:13 +00:00
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
...
llvm-svn: 35479
2007-03-29 21:38:31 +00:00
8f592160c0
Add support for hidden visibility to darwin/arm.
...
llvm-svn: 35448
2007-03-29 07:49:34 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
...
llvm-svn: 35381
2007-03-27 16:19:21 +00:00
7dbbd00b06
findRegisterUseOperand() changed.
...
llvm-svn: 35366
2007-03-26 22:41:48 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
cba9538499
Updated.
...
llvm-svn: 35229
2007-03-20 22:32:39 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
...
mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9e7b838469
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
...
llvm-svn: 35207
2007-03-20 08:11:30 +00:00
39eb62ea3b
New entry.
...
llvm-svn: 35206
2007-03-20 08:10:17 +00:00
61f39d186c
Added MRegisterInfo hook to re-materialize an instruction.
...
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
f806e1cdbc
fix indentation
...
llvm-svn: 35202
2007-03-20 02:25:53 +00:00
8447d34903
fix obvious comment bug
...
llvm-svn: 35196
2007-03-20 00:30:56 +00:00
9bb01c9f4f
Fix naming inconsistencies.
...
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
...
llvm-svn: 35161
2007-03-19 07:09:02 +00:00
25d4052af6
Only ARMv6 has BSWAP.
...
Fix MultiSource/Applications/aha test.
llvm-svn: 35128
2007-03-16 22:54:16 +00:00
0e34d6af6b
Added isLegalAddressExpression(). Only allows X +/- C for now.
...
llvm-svn: 35122
2007-03-16 08:43:56 +00:00
72a8bcf238
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
507eefa757
Zero is always a legal AM immediate.
...
llvm-svn: 35087
2007-03-13 20:37:59 +00:00
818242bbaf
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
...
llvm-svn: 35077
2007-03-13 01:20:42 +00:00
2150b9286f
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
...
llvm-svn: 35075
2007-03-12 23:30:29 +00:00
09663aeac7
Minor stuff.
...
llvm-svn: 35049
2007-03-09 19:46:06 +00:00
31ef0ab7cf
Add comments about LSR / ARM.
...
llvm-svn: 35048
2007-03-09 19:35:33 +00:00
603f3094eb
Unfinished work and ideas related to register scavenger.
...
llvm-svn: 35047
2007-03-09 19:34:51 +00:00
368faf9acd
apply comments from review of last patch
...
llvm-svn: 35045
2007-03-09 19:18:59 +00:00
af0cff2671
Add some observations from CoreGraphics benchmark. Remove register
...
scavenging todo item, since it is now implemented.
llvm-svn: 35044
2007-03-09 17:58:17 +00:00
ea28fc5dc4
Implement inline asm modifier c.
...
llvm-svn: 35035
2007-03-08 22:42:46 +00:00
63170b6959
Fix a typo.
...
llvm-svn: 35030
2007-03-08 21:59:30 +00:00
ddf082082c
Putting more constants which do not contain relocations into .literal{4|8|16}
...
llvm-svn: 35026
2007-03-08 08:31:54 +00:00
e94a2f8026
Change register allocation order to Dale's suggestion.
...
llvm-svn: 35021
2007-03-08 02:56:40 +00:00
977195e912
Bug fix. Not advancing the register scavenger iterator correctly.
...
llvm-svn: 35020
2007-03-08 02:55:08 +00:00
d918477ac3
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
...
sections.
llvm-svn: 35017
2007-03-08 01:25:25 +00:00
f030f2d628
Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
...
llvm-svn: 35010
2007-03-07 20:30:36 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
17cdad0687
ARM always use register scavenger. No longer reserves R12.
...
llvm-svn: 34999
2007-03-07 02:46:23 +00:00
2818fdd019
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
...
llvm-svn: 34998
2007-03-07 02:38:05 +00:00
67038e7a8b
Fix one more Thumb eliminateFrameIndex bug.
...
llvm-svn: 34990
2007-03-07 00:12:18 +00:00
5ed781b0db
Register scavenging is now on by default for ARM.
...
llvm-svn: 34987
2007-03-06 22:02:53 +00:00
41bc2fd242
Make load / store optimizer use register scavenger.
...
llvm-svn: 34986
2007-03-06 21:59:20 +00:00
d28de6700b
Code clean up. Prepare to use register scavenger.
...
llvm-svn: 34976
2007-03-06 18:02:41 +00:00
4783ae8ac1
Scavenge a register using the register scavenger when needed.
...
llvm-svn: 34966
2007-03-06 10:03:56 +00:00
e7ec3bc7bc
Use new SDIselParamAttr enumeration. This removes "magick" constants
...
from formal attributes' flags processing.
llvm-svn: 34963
2007-03-06 08:12:33 +00:00
f10769dda7
Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS.
...
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.
llvm-svn: 34931
2007-03-05 17:59:58 +00:00
32bc81341b
eliminate unnecessary reset of SP in epilog on darwin
...
llvm-svn: 34824
2007-03-02 01:17:17 +00:00
2c0fd3ee4c
Use a spilled free callee-saved register as scratch register.
...
llvm-svn: 34785
2007-03-01 08:57:52 +00:00
6f059e3e0a
- Track which callee-saved registers are spilled.
...
- Some code clean up.
llvm-svn: 34783
2007-03-01 08:26:31 +00:00
677bb3b460
Switch from std::vector<bool> to BitVector.
...
llvm-svn: 34781
2007-03-01 07:52:44 +00:00
65c75b57d4
Get rid of verboten <iostream> include.
...
llvm-svn: 34777
2007-03-01 06:05:39 +00:00
962fa8eb9a
Changes requested in review of last pass. Also pulled isThumb into a
...
member, instead of resetting in every function that uses it.
llvm-svn: 34764
2007-02-28 23:20:38 +00:00
f6ca943638
Doh. ARM::PC is obvious a reserved register.
...
llvm-svn: 34763
2007-02-28 23:12:34 +00:00
440995bd9a
Add intelligence about where to break large blocks.
...
llvm-svn: 34755
2007-02-28 18:41:23 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
...
llvm-svn: 34711
2007-02-28 00:59:19 +00:00
9049cd72e6
Temporary: make R12 available in ARM mode if RegScavenger is being used.
...
llvm-svn: 34709
2007-02-28 00:22:44 +00:00
30508919c8
Start making use of RegScavenger.
...
llvm-svn: 34708
2007-02-28 00:21:58 +00:00
95ae95a6a6
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
...
llvm-svn: 34707
2007-02-28 00:21:17 +00:00
ee8aca0cfa
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function.
...
llvm-svn: 34701
2007-02-27 23:03:55 +00:00
71a7271b8b
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info.
...
llvm-svn: 34692
2007-02-27 21:12:35 +00:00
c2f3d015e0
cosmetic changes from review of last patch. obvious
...
llvm-svn: 34598
2007-02-25 18:31:31 +00:00
e80e31eada
remove crediting of Evan Cheng and me.
...
llvm-svn: 34568
2007-02-25 01:42:36 +00:00
01ee5750f4
Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this
...
from README.
When no water available, use end of block if in range. (More to do here.)
llvm-svn: 34563
2007-02-25 00:47:03 +00:00
0eb70ebbe5
bugfix: SP wasn't updated for varargs when frame pointer was eliminated.
...
llvm-svn: 34537
2007-02-23 21:53:48 +00:00
3e906c48d3
Fix stack alignment in functions with varargs.
...
llvm-svn: 34532
2007-02-23 20:32:57 +00:00
e18b13b213
rewrite of constant islands
...
llvm-svn: 34523
2007-02-23 05:02:36 +00:00
9f8301413c
Added -march=thumb; removed -enable-thumb.
...
llvm-svn: 34521
2007-02-23 03:14:31 +00:00
15af662314
Add option to turn on register scavenger; By default, spills kills the register being stored.
...
llvm-svn: 34514
2007-02-23 01:09:11 +00:00
e0008e23cf
Simplify lowering and selection of exception ops.
...
llvm-svn: 34488
2007-02-22 14:56:36 +00:00
3796abea0f
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
9865be6d40
Added getReservedRegs().
...
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
50c6a8c3a1
Add space between // and the comment.
...
llvm-svn: 34246
2007-02-13 20:06:15 +00:00
048e16ff8f
Add ABI information to ARM subtarget.
...
llvm-svn: 34245
2007-02-13 19:52:28 +00:00
603f201cba
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
...
llvm-svn: 34241
2007-02-13 14:07:13 +00:00
540f5e0d41
These vectors are frequently large. Use std::vector instead.
...
llvm-svn: 34109
2007-02-09 23:59:14 +00:00
8b7700f146
Add reference counting to constantpool entries. Delete the unused ones.
...
llvm-svn: 34105
2007-02-09 20:54:44 +00:00
2ff4c973b1
isLowRegister() expects input is a physical register.
...
llvm-svn: 34013
2007-02-07 21:44:33 +00:00
cca9b1d768
Rename.
...
llvm-svn: 34011
2007-02-07 21:24:09 +00:00
ec4c67f0a7
If sp offset will be materialized in a register. Clear the offset field of str / ldr.
...
llvm-svn: 34010
2007-02-07 21:19:58 +00:00
62aef236de
Get rid of references to iostream.
...
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
b216ea1aa6
New entry.
...
llvm-svn: 34000
2007-02-07 09:22:15 +00:00
78c5a9422d
In thumb mode, R3 is reserved, but it can be live in to the function. If
...
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!
llvm-svn: 33999
2007-02-07 09:17:36 +00:00
2ff0d3a2ab
Update
...
llvm-svn: 33998
2007-02-07 08:37:57 +00:00
b5519b5361
- If fp (r7) is used to reference stack objects, use [r, r] address mode.
...
- If there is a dynamic alloca, in the epilogue, restore the value of sp
using r7 - offset.
- Other bug fixes.
llvm-svn: 33997
2007-02-07 08:37:31 +00:00
12cf8ddaea
eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's.
...
llvm-svn: 33975
2007-02-07 02:44:23 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
...
llvm-svn: 33971
2007-02-07 00:06:56 +00:00
a974031ebd
Select add FI, c correctly.
...
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
ea3308aef0
foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.
...
llvm-svn: 33958
2007-02-06 06:13:29 +00:00
2fc792f86b
eliminateFrameIndex() bug when frame pointer is used as base register.
...
llvm-svn: 33945
2007-02-06 00:23:31 +00:00
650d0672f7
- Store val, [sp, c] must be selected to tSTRsp.
...
- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
llvm-svn: 33944
2007-02-06 00:22:06 +00:00
456db39ea9
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
...
llvm-svn: 33832
2007-02-03 09:11:58 +00:00
4b6c8f7f5e
Fix comments.
...
llvm-svn: 33831
2007-02-03 08:53:01 +00:00
36d559d369
- Branch max. displacement calculation bug.
...
- Add debugging info.
llvm-svn: 33811
2007-02-03 02:08:34 +00:00
b739f7d337
bugfix: SP isn't resetted when function has FP and there is no spills.
...
llvm-svn: 33800
2007-02-02 23:08:40 +00:00
f089c99f1d
Another thumb large stack offset codegen bug.
...
llvm-svn: 33795
2007-02-02 21:08:39 +00:00
d9d94700a4
Use MBB.empty() instead of MBB.size() for speed.
...
llvm-svn: 33789
2007-02-02 19:09:19 +00:00
3ad22567b3
Watch out for empty BB.
...
llvm-svn: 33788
2007-02-02 18:49:02 +00:00
fda6550545
Ugh. Only meant to do this in thumb mode.
...
llvm-svn: 33780
2007-02-02 08:58:48 +00:00
2d5b4ac38f
add a note
...
llvm-svn: 33778
2007-02-02 04:36:46 +00:00
48b094d9dd
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant.
...
llvm-svn: 33775
2007-02-02 01:53:26 +00:00
9b9e4ae796
Thumb does not have clz.
...
llvm-svn: 33773
2007-02-01 23:34:03 +00:00
2c355da986
Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll)
...
llvm-svn: 33763
2007-02-01 21:43:53 +00:00
fd522996c8
Pasto. Lots of it.
...
llvm-svn: 33762
2007-02-01 20:44:52 +00:00
903e01d407
Fix .thumb_func directive on linux.
...
llvm-svn: 33759
2007-02-01 18:25:34 +00:00
Evan Cheng