0aa8f0a549
Added -disable-mmx using a patch from Preston Gurd.
...
llvm-svn: 59901
2008-11-23 04:37:22 +00:00
0be0339baa
CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was it
...
ever conceived to occur).
llvm-svn: 59891
2008-11-22 23:50:42 +00:00
bff4b37af5
Make a convenient helper for printing offsets.
...
llvm-svn: 59872
2008-11-22 16:15:34 +00:00
c6918c1ffa
CellSPU:
...
(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.
llvm-svn: 59790
2008-11-21 02:56:16 +00:00
3726019aa3
CellSPU:
...
(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.
llvm-svn: 59734
2008-11-20 16:36:33 +00:00
e15a540071
Allow XMM2 and XMM3 to be used for non ABI compliant code.
...
llvm-svn: 59720
2008-11-20 07:48:19 +00:00
a7521ee3df
CellSPU: Custom lower truncating stores of i8 to i1 (should not have been
...
promote), fix signed conversion of indexed offsets.
llvm-svn: 59707
2008-11-20 05:01:09 +00:00
e361f08ab0
CellSPU: Adjust spacing/tabulation
...
llvm-svn: 59703
2008-11-20 04:26:21 +00:00
5f23e9fe73
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
...
llvm-svn: 59696
2008-11-20 02:25:51 +00:00
59213d64e5
Eliminate a compile time warning.
...
llvm-svn: 59678
2008-11-19 23:21:33 +00:00
dfb97383d5
Eliminate a compile time warning.
...
llvm-svn: 59677
2008-11-19 23:21:11 +00:00
60cb69e665
Experimental post-pass scheduling support. Post-pass scheduling
...
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
llvm-svn: 59676
2008-11-19 23:18:57 +00:00
7455d45ba2
CMake: Removed source file from lib/Target/PIC16/CMakeLists.txt.
...
llvm-svn: 59655
2008-11-19 18:42:25 +00:00
ef5e6934cb
CellSPU: Do not custom lower i1 stores, rely on type legalization to do the
...
right thing and promote the store to i8.
llvm-svn: 59648
2008-11-19 17:45:08 +00:00
0daa1b4a94
<rdar://problem/6351057>
...
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.
llvm-svn: 59644
2008-11-19 17:19:35 +00:00
3462c8ecda
Temporary check-in for Duncan to demonstrate CellSPU store problem.
...
llvm-svn: 59637
2008-11-19 15:24:16 +00:00
7e8bf3422f
Forgot to add this in the previous commit.
...
llvm-svn: 59623
2008-11-19 12:12:49 +00:00
5c63cf8bfd
Fixed build warnings.
...
llvm-svn: 59621
2008-11-19 11:27:59 +00:00
2ae21ee517
Added a more function PIC16 backend. However to get this working a patch in
...
ExpandIntegerOperand (LegalizeIntegerTypes.cpp) is needed which is yet to be reworked and submitted.
llvm-svn: 59617
2008-11-19 11:00:54 +00:00
c8d2b0135a
Don't set neverHasSideEffects on x86's divide instructions, since
...
they trap on divide-by-zero, and this side effect is otherwise
unmodeled.
llvm-svn: 59551
2008-11-18 21:29:14 +00:00
0b2732598c
Add more const qualifiers. This fixes build breakage from r59540.
...
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
aae3a4f864
Move some former testcases (low-probability codegen
...
optimizations) into this wishlist.
llvm-svn: 59455
2008-11-17 18:56:34 +00:00
ba4eb2a9db
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
...
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
llvm-svn: 59378
2008-11-15 21:36:30 +00:00
9c205bf03c
Fix fuitos encoding.
...
llvm-svn: 59344
2008-11-15 00:40:57 +00:00
30f6f8fdad
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
...
llvm-svn: 59314
2008-11-14 20:09:11 +00:00
80cd21dba6
Remove unneeded stuff from GRAD register class.
...
llvm-svn: 59311
2008-11-14 18:10:48 +00:00
0f802ba33e
[XCore] Remove whitespace in the description used when
...
registering XCoreTargetMachine.
llvm-svn: 59308
2008-11-14 16:19:56 +00:00
5fe5933909
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
...
these operations if ladd/lsub are not available on the current
subtarget.
llvm-svn: 59305
2008-11-14 15:59:19 +00:00
d16b37efae
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
...
bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
fabdcce677
Handle the rest of pseudo instructions.
...
llvm-svn: 59275
2008-11-13 23:36:57 +00:00
ea68423998
Lazy compilation callback save / restore VFP registers.
...
llvm-svn: 59274
2008-11-13 23:28:54 +00:00
bee1ad9707
Extend InlineAsm::C_Register to allow multiple specific registers
...
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
llvm-svn: 59266
2008-11-13 21:52:36 +00:00
935963de81
Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.
...
llvm-svn: 59258
2008-11-13 19:22:28 +00:00
320902bcfc
fsub{d|s} encoding bugs.
...
llvm-svn: 59234
2008-11-13 07:59:48 +00:00
4af89f7e7d
Missed a break statement.
...
llvm-svn: 59231
2008-11-13 07:46:59 +00:00
2666f59322
Fix pre- and post-indexed load / store encoding bugs.
...
llvm-svn: 59230
2008-11-13 07:34:59 +00:00
88ba5f0b96
Move the code that inserts X87 FP_REG_KILL instructions from a
...
special-purpose hook to a new pass. Also, add check to see if any
x87 virtual registers are used, to avoid doing any work in the
common case that no x87 code is needed.
llvm-svn: 59190
2008-11-12 22:55:05 +00:00
287a25d636
Remove the incorrect assertion. We don't have enough information before relocation to set U bit.
...
llvm-svn: 59170
2008-11-12 21:37:59 +00:00
45d030a05a
Address mode immediate offset has already been divided by 4.
...
llvm-svn: 59117
2008-11-12 08:21:12 +00:00
052f20d3b1
Fix a VFP binary arithmetic instruction encoding bug.
...
llvm-svn: 59116
2008-11-12 08:14:21 +00:00
2836d91630
Fix address mode 3 immediate offset mode encoding.
...
llvm-svn: 59109
2008-11-12 07:34:37 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
...
llvm-svn: 59107
2008-11-12 07:18:38 +00:00
4b6c7efbde
Fix VFP conversion instruction encodings.
...
llvm-svn: 59104
2008-11-12 06:41:41 +00:00
a0e2f26320
Fix encoding of single-precision VFP registers.
...
llvm-svn: 59102
2008-11-12 02:19:38 +00:00
bfcee5b863
VFP fld / fst immediate field is multiplied by 4.
...
llvm-svn: 59100
2008-11-12 01:02:24 +00:00
7d8b884b12
This shouldn't be necessary
...
llvm-svn: 59090
2008-11-11 23:19:51 +00:00
97ccab888a
Fix FMDRR encoding.
...
llvm-svn: 59088
2008-11-11 22:46:12 +00:00
ad519bbe54
Handle floating point constpool_entry's.
...
llvm-svn: 59087
2008-11-11 22:19:31 +00:00
8cbbcb1f2f
Encode VFP load / store instructions.
...
llvm-svn: 59084
2008-11-11 21:48:44 +00:00
38c9a14a88
Encode VFP conversion instructions.
...
llvm-svn: 59074
2008-11-11 19:40:26 +00:00
2d1937ede5
Add a README entry.
...
llvm-svn: 59052
2008-11-11 17:35:52 +00:00
a08c2905ad
CMake: corrected split of Alpha and Sparc AsmPrinters.
...
llvm-svn: 59050
2008-11-11 17:10:13 +00:00
03e084d482
Separate sparc asmprinter. This should unbreak the native build
...
llvm-svn: 59047
2008-11-11 16:42:57 +00:00
f4caceb668
Separate alpha asmprinter. This should unbreak native build.
...
llvm-svn: 59046
2008-11-11 16:42:17 +00:00
059c4fa8d8
The 32-bit displacement field in an x86 address is signed. Arrange for it
...
to be sign-extended when it is promoted to 64 bits for intermediate
offset calculations. The offset calculations are done as uint64_t so that
overflow conditions are well defined.
This fixes a problem which is currently hidden by the x86 AsmPrinter but
which was exposed by r58917 (which is temporarily reverted). See PR3027
for details.
llvm-svn: 59044
2008-11-11 15:52:29 +00:00
2126a6d3c4
fix another libgcc blocker
...
llvm-svn: 59026
2008-11-11 06:06:07 +00:00
aab89ca749
Unbreak the buildbot and back out (inadvertant) casting edits in CellSPU
...
backend.
llvm-svn: 59018
2008-11-11 03:06:06 +00:00
ac2af2fdb2
Encode VFP arithmetic instructions.
...
llvm-svn: 59016
2008-11-11 02:11:05 +00:00
abad22cf45
CellSPU: Fix bug 3606, as well as some ongoing work.
...
llvm-svn: 59009
2008-11-10 23:43:06 +00:00
02771dc473
Correct PIC function stub codegen.
...
llvm-svn: 59006
2008-11-10 23:14:47 +00:00
d3b33fea65
Fix indentation.
...
llvm-svn: 59004
2008-11-10 22:09:58 +00:00
58fb9135e2
Added CONVERT_RNDSAT (conversion with rounding and saturation) SDNode to
...
support targets that support these conversions. Users should avoid using
this node as the current targets don't generating code for it.
llvm-svn: 59001
2008-11-10 20:54:11 +00:00
9f3058f3be
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
...
llvm-svn: 58949
2008-11-10 01:08:07 +00:00
cfb3bc4a45
Typo fix
...
llvm-svn: 58928
2008-11-09 02:54:13 +00:00
9833d8c369
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
...
and breaks llvm-gcc
llvm-svn: 58926
2008-11-08 23:05:05 +00:00
4829941a51
CMake: corrected library target name for dependency: LLVMCellSPU ->
...
LLVMCellSPUCodeGen.
llvm-svn: 58925
2008-11-08 21:23:15 +00:00
676e5194d0
CMake: Reflected changes on the CellSPU target build. May require a
...
clean start.
llvm-svn: 58924
2008-11-08 20:37:19 +00:00
b200b648c4
Fixed a pasto.
...
llvm-svn: 58923
2008-11-08 20:34:18 +00:00
a872e5af8a
CellSPU: Bring SPU's assembly printer more in-line with current LLVM code
...
structure. Assembly printer now outputs the correct section for strings.
llvm-svn: 58921
2008-11-08 18:59:02 +00:00
09f51d1fd4
Factor out offset printing code into generic AsmPrinter.
...
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
llvm-svn: 58917
2008-11-08 17:21:38 +00:00
5a48f232f7
The Index field of an AttributeWithIndex is of type unsigned, not uint16_t.
...
llvm-svn: 58908
2008-11-08 15:36:01 +00:00
09991ada2d
StoreInst does not produce any result thus it's useless to create new
...
variable for it. This greatly reduces amount of unused variables in
llvm2cpp-generated code
llvm-svn: 58905
2008-11-08 12:58:07 +00:00
436bdcdcca
Moved InvalidateInstructionCache to ARMJITInfo::emitFunctionStub which knows size of stub.
...
llvm-svn: 58899
2008-11-08 08:16:49 +00:00
b31a717527
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
...
llvm-svn: 58897
2008-11-08 08:02:53 +00:00
98161f5f34
Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
...
llvm-svn: 58896
2008-11-08 07:38:22 +00:00
bb373c4637
Fix relocation for calls to external symbols.
...
llvm-svn: 58893
2008-11-08 07:22:33 +00:00
1ccbbc3d07
CellSPU: Fix prologue/epilogue emission when function contains calls but
...
theframe size is 0; the prologue and epilogue should be emitted in this case.
llvm-svn: 58890
2008-11-08 05:16:20 +00:00
077c8f8832
Skip over two-address use operands.
...
llvm-svn: 58883
2008-11-08 01:44:13 +00:00
ffdd91e3b8
Handle ARM machine constantpool entry with non-lazy ptr.
...
llvm-svn: 58882
2008-11-08 01:31:27 +00:00
454ff53d58
Use ARMFunctionInfo to track number of constpool entries and jumptables.
...
llvm-svn: 58877
2008-11-08 00:51:41 +00:00
ef4d78ba67
More code clean up.
...
llvm-svn: 58872
2008-11-07 22:57:53 +00:00
160be0ffda
Make FP tests requiring two compares work on PPC (PR 642).
...
This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
llvm-svn: 58871
2008-11-07 22:54:33 +00:00
8467e2459a
Get PIC jump table working.
...
llvm-svn: 58869
2008-11-07 22:30:53 +00:00
cb0df597e0
Flush the raw_ostream after emitting the assembly for a function.
...
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
llvm-svn: 58859
2008-11-07 19:49:17 +00:00
3219819ffe
Fix compile warnings.
...
llvm-svn: 58840
2008-11-07 11:21:09 +00:00
3395d4485d
CellSPU: Ensure that C strings are always put in the .rodata section
...
llvm-svn: 58839
2008-11-07 11:06:44 +00:00
ca08e0645a
Add XCore backend.
...
llvm-svn: 58838
2008-11-07 10:59:00 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
...
llvm-svn: 58836
2008-11-07 09:06:08 +00:00
34d93f8572
Teach CellSPU about ELF sections and new section emitter classes.
...
NB: This is likely to need more work.
llvm-svn: 58832
2008-11-07 04:36:25 +00:00
98dc53e926
Encode misc arithmetic instructions.
...
llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
...
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
...
- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
...
llvm-svn: 58800
2008-11-06 08:47:38 +00:00
9a8d60a7c0
Widening cleanup
...
llvm-svn: 58796
2008-11-06 05:31:54 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
...
llvm-svn: 58793
2008-11-06 03:35:07 +00:00
b870fd8874
Fix so_imm encoding bug; add support for MOVi2pieces.
...
llvm-svn: 58790
2008-11-06 02:25:39 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
...
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
...
llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
...
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
7a638a8c7e
Reintroduce a comment that was removed with the AddToISelQueue
...
changes.
llvm-svn: 58760
2008-11-05 17:16:24 +00:00
bfd58d87f3
Test commit, add Makefile for XCore target, more to follow.
...
llvm-svn: 58755
2008-11-05 09:53:58 +00:00
27889ab29f
Add more vector move low and zero-extend patterns.
...
llvm-svn: 58752
2008-11-05 06:04:51 +00:00
3cd5e8c97b
Indentation.
...
llvm-svn: 58750
2008-11-05 06:03:38 +00:00
f14b77ebf1
Eliminate the ISel priority queue, which used the topological order for a
...
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
llvm-svn: 58748
2008-11-05 04:14:16 +00:00
fd820528ab
Use getTargetConstant instead of getConstant for nodes that should not be visited
...
by isel and potentially forced into registers.
llvm-svn: 58747
2008-11-05 02:06:09 +00:00
132de1983f
Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X
...
indirect gv reference. Please don't call it lazy.
llvm-svn: 58746
2008-11-05 01:50:32 +00:00
e3827d9061
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
...
llvm-svn: 58725
2008-11-04 22:19:55 +00:00
297b32a367
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
...
llvm-svn: 58714
2008-11-04 19:57:48 +00:00
4eaff40147
Debug output tweak.
...
llvm-svn: 58708
2008-11-04 17:58:53 +00:00
453844c352
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
...
llvm-svn: 58707
2008-11-04 17:57:07 +00:00
9340be4641
For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
...
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.
llvm-svn: 58688
2008-11-04 09:30:48 +00:00
2299c99d79
Stylistic change.
...
llvm-svn: 58683
2008-11-04 06:10:06 +00:00
6dd08b6604
Handle ARM machine constantpool entries.
...
llvm-svn: 58671
2008-11-04 00:50:32 +00:00
b9110e7fbb
The ANDMask node folds to a constant, and isn't the node that needs to
...
have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.
llvm-svn: 58655
2008-11-03 23:43:55 +00:00
f60e5aaaac
Remove a dead switch statement.
...
llvm-svn: 58644
2008-11-03 21:26:52 +00:00
3620e685b5
Minor code restructuring. No functionality change.
...
llvm-svn: 58643
2008-11-03 21:02:39 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
...
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
ac41d9f5d8
Refactor various TargetAsmInfo subclasses' TargetMachine members away
...
adding a TargetMachine member to the base TargetAsmInfo class instead.
llvm-svn: 58624
2008-11-03 18:22:42 +00:00
03f5122c6c
Whitespace fixes. No functionality change.
...
llvm-svn: 58539
2008-10-31 21:26:08 +00:00
83bf3de134
Add comment.
...
llvm-svn: 58533
2008-10-31 19:56:03 +00:00
20dbb3bcad
Use better data structure for ConstPoolId2AddrMap.
...
llvm-svn: 58532
2008-10-31 19:55:13 +00:00
44994e0c77
Actually make debug output understandable.
...
llvm-svn: 58529
2008-10-31 19:15:52 +00:00
ef89465c9f
x86_64 rip-relative and magic mode address
...
llvm-svn: 58528
2008-10-31 19:13:42 +00:00
8fce66a47c
Forgot this in last commit.
...
llvm-svn: 58527
2008-10-31 19:11:09 +00:00
467e6e8093
Encode PICADD; some code clean up.
...
llvm-svn: 58526
2008-10-31 19:10:44 +00:00
d2bc13380f
Revert r58489. It isn't correct for all cases.
...
llvm-svn: 58523
2008-10-31 18:30:19 +00:00
7e8202fce4
Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm.
...
llvm-svn: 58517
2008-10-31 16:52:57 +00:00
6d70df0b05
Don't skip over all "terminator" instructions when determining where to put the
...
callee-saved restore code. It could skip over conditional jumps
accidentally. Instead, just skip the "return" instructions.
llvm-svn: 58489
2008-10-31 04:00:23 +00:00
99cdf8893e
Use MOVSSmr instead of EXTRACTPSmr in the case of extracting
...
vector element 0 for a store, as it's smaller and faster.
llvm-svn: 58483
2008-10-31 00:57:24 +00:00
c696ef9b11
I think we got non-machine specific constpool entries covered.
...
llvm-svn: 58474
2008-10-30 23:43:36 +00:00
1310574b0f
Shift amounts should have type getShiftAmountTy
...
(i32 for PPC, not i8). Correct this, and some
formatting while there.
llvm-svn: 58451
2008-10-30 19:28:32 +00:00
0852f48d1d
Shift amounts should have the type given by
...
getShiftAmountTy (i32 in the case of CellSPU).
llvm-svn: 58449
2008-10-30 19:24:28 +00:00
66cff408ff
ARM JIT should observe -relocation-model command line option.
...
llvm-svn: 58433
2008-10-30 16:10:54 +00:00
58c3794c27
Add initial support for vector widening. Logic is set to widen for X86.
...
One will only see an effect if legalizetype is not active. Will move
support to LegalizeType soon.
llvm-svn: 58426
2008-10-30 08:01:45 +00:00
487c43412d
Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stack
...
so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.
N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.
llvm-svn: 58415
2008-10-30 01:51:48 +00:00
19d64ba8bf
Correct way to handle CONSTPOOL_ENTRY instructions.
...
llvm-svn: 58409
2008-10-29 23:55:43 +00:00
de9dbc5584
Add debugging support.
...
llvm-svn: 58408
2008-10-29 23:55:17 +00:00
534ac08ebd
Fix PEXTRQ encoding
...
llvm-svn: 58403
2008-10-29 23:07:17 +00:00
98aa9d3e49
Add a RM pseudoreg for the rounding mode, which
...
allows ppcf128->int conversion to work with
DeadInstructionElimination. This is now turned
off but RM is harmless. It does not do a complete
job of modeling the rounding mode.
Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now. Eventually it should go back in and the
other problems fixed where they're broken.
llvm-svn: 58391
2008-10-29 18:26:45 +00:00
ff2b4948ce
Support for constant islands in the ARM JIT.
...
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the
instruction stream.
Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.
For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.
llvm-svn: 58338
2008-10-28 18:25:49 +00:00
4068a7f31e
Fix darwin ppc llvm-gcc build breakage: intercept
...
ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG. This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes. Probably PPC should
simply custom lower the original conversion.
llvm-svn: 58329
2008-10-28 15:00:32 +00:00
38461f6b2f
Fix a nasty miscompilation of 176.gcc on linux/x86 where we synthesized
...
a memset using 16-byte XMM stores, but where the stack realignment code
didn't work. Until it does (PR2962) disable use of xmm regs in memcpy
and memset formation for linux and other targets with insufficiently
aligned stacks.
This is part of PR2888
llvm-svn: 58317
2008-10-28 05:49:35 +00:00
ce2a938186
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
...
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
llvm-svn: 58278
2008-10-27 21:56:29 +00:00
f713722975
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
...
llvm-svn: 58230
2008-10-27 07:14:50 +00:00
191453174d
Move the code that adds the DeadMachineInstructionElimPass from
...
target-independent code to target-specific code. This prevents it
from running on targets that aren't using fast-isel.
In addition to saving compile time, this addresses the problem
that not all targets are prepared for it. In order to use this
pass, all instructions must declare all their fixed uses and
defs of physical registers.
llvm-svn: 58144
2008-10-25 17:46:52 +00:00
5457ce9ac3
Support for allocation of TLS variables in the JIT. Allocation of a global
...
variable is moved to the execution engine. The JIT calls the TargetJITInfo
to allocate thread local storage. Currently, only linux/x86 knows how to
allocate thread local global variables.
llvm-svn: 58142
2008-10-25 15:41:43 +00:00
db30612fc4
Generate code for TLS instructions.
...
llvm-svn: 58141
2008-10-25 15:22:06 +00:00
9ba4650b76
CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.
...
llvm-svn: 58133
2008-10-25 03:40:32 +00:00
71f361e758
Mark MFCR as reading all condition code registers.
...
Prevents some more overzealous deletions (mostly
in AltiVec code).
llvm-svn: 58121
2008-10-24 22:08:01 +00:00
3863f8e725
Rewrite logic to figure out whether LR needs to
...
be saved/restored in the prolog/epilog. We need
to do this iff something in the function stores
into it.
llvm-svn: 58116
2008-10-24 21:24:23 +00:00
33986d8f17
move the note to the correct README
...
llvm-svn: 58104
2008-10-24 19:23:07 +00:00
fcaae54669
add note about va_arg code on x86 and x86-64
...
llvm-svn: 58103
2008-10-24 19:20:05 +00:00
014f5bbaad
Fix translateX86CC: if SetCCOpcode is SETULE and
...
LHS is a foldable load, then LHS and RHS are swapped
and SetCCOpcode is changed to SETUGT. But the later
code is expecting operands to be the wrong way round
for SETUGT, but they are not in this case, resulting
in an inverted compare. The solution is to move the
load normalization before the correction for SETUGT.
This bug was tickled by LegalizeTypes which happened
to legalize the testcase slightly differently to
LegalizeDAG.
llvm-svn: 58092
2008-10-24 13:03:10 +00:00
712886f561
Fix constant-offset emission for x86-64 absolute addresses. This
...
fixes a bunch of test-suite JIT failures on x86-64 in
-relocation-model=static mode.
llvm-svn: 58066
2008-10-24 01:57:54 +00:00
e395d78657
Mark defs and uses of CTR and LR correctly.
...
Prevents DeadMachineInstructionElim from thinking
things like MTCTR are dead (fixes massive
testsuite breakage at -O0).
llvm-svn: 58043
2008-10-23 20:41:28 +00:00
1ecf1fd5c8
remove extraneous #ifdef's
...
llvm-svn: 58006
2008-10-22 22:27:51 +00:00
f6655a9e79
Remove allocation of unused stack slot.
...
llvm-svn: 57987
2008-10-22 17:26:06 +00:00
5ee1dde8fa
Get this working with LegalizeTypes: (1) don't
...
assume that i64 has been turned into a BUILD_PAIR
node (when called from LegalizeTypes this hasn't
happened yet) and don't use a vector shuffle mask
with an illegal element type.
llvm-svn: 57972
2008-10-22 11:24:12 +00:00
35b40f8c2f
Fix PR2907 by digging through constant expressions to find FP constants that
...
are their operands.
llvm-svn: 57956
2008-10-22 04:53:16 +00:00
f3c03b02dc
CMake: Turned some libraries into partially linked objects. Corrected
...
names of LLVMCore and ARMCodeGen.
llvm-svn: 57943
2008-10-22 02:51:53 +00:00
cf4607fcce
Adjust comments for pedantic satisfaction.
...
llvm-svn: 57940
2008-10-22 00:02:32 +00:00
3d7ece1acb
Add comments to explain uint64->f64 algorithm,
...
well, sort of. (Algorithm by Ian Ollmann.)
llvm-svn: 57932
2008-10-21 23:07:49 +00:00
28929589e7
Add an SSE2 algorithm for uint64->f64 conversion.
...
The same one Apple gcc uses, faster. Also gets the
extreme case in gcc.c-torture/execute/ieee/rbug.c
correct which we weren't before; this is not
sufficient to get the test to pass though, there
is another bug.
llvm-svn: 57926
2008-10-21 20:50:01 +00:00
4ddf7a4c22
Implement the optimized FCMP_OEQ/FCMP_UNE code for x86 fast-isel.
...
llvm-svn: 57915
2008-10-21 18:24:51 +00:00
cfebc18d7c
use pre-UAL mnemonics for push/pop for compilaton callback function
...
llvm-svn: 57911
2008-10-21 16:54:12 +00:00
c14e5227f0
Disable constant-offset folding for PowerPC, as the PowerPC target
...
isn't yet prepared for it.
llvm-svn: 57886
2008-10-21 03:41:46 +00:00
269246b034
Don't create TargetGlobalAddress nodes with offsets that don't fit
...
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.
Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.
llvm-svn: 57885
2008-10-21 03:38:42 +00:00
97d95d6d85
Optimized FCMP_OEQ and FCMP_UNE for x86.
...
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 03:29:32 +00:00
c835458da9
When the coalescer is doing rematerializing, have it remove
...
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.
Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.
These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.
llvm-svn: 57872
2008-10-21 03:24:31 +00:00
9396051e3d
Update the stub and callback code to handle lazy compilation. The stub
...
is re-written by the callback to branch directly to the compiled code
in future invocations.
Added back in range-based memory permission functions for the updating of
the stub on Darwin.
llvm-svn: 57846
2008-10-20 21:39:23 +00:00
1d20ab5784
Have X86 custom lowering for LegalizeTypes use
...
LowerOperation if it doesn't know what else to do.
This methods should probably be factorized some,
but this is good enough for the moment. Have
LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather
than assuming the operand is a BUILD_PAIR (if it
is then getNode will automagically simplify the
EXTRACT_ELEMENT). This way LowerATOMIC_BINARY_64
usable from LegalizeTypes.
llvm-svn: 57831
2008-10-20 15:56:33 +00:00
2fe6bee5b6
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
...
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 02:06:02 +00:00
209fc26462
This is now partly done.
...
llvm-svn: 57734
2008-10-17 21:39:27 +00:00
b1d8d6ecff
This is done.
...
llvm-svn: 57733
2008-10-17 21:38:40 +00:00
0fcc89b596
Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.
...
llvm-svn: 57723
2008-10-17 21:02:22 +00:00
8e2ef196ae
add support for 128 bit inputs on both x86-64 and x86-32.
...
llvm-svn: 57709
2008-10-17 18:15:05 +00:00
c7e65f4377
Fix a bug where the x86 backend would reject 64-bit r constraints when
...
in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
llvm-svn: 57704
2008-10-17 17:59:52 +00:00
27c3702267
Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.
...
llvm-svn: 57692
2008-10-17 17:14:20 +00:00
9e23d746bf
getX86RegNum has long been moved to X86RegisterInfo.
...
llvm-svn: 57691
2008-10-17 17:12:18 +00:00
7e9e3b3d4b
add some simple hacky long double support for the CBE. This
...
should work for intel long double, but ppc long double aborts
in convert.
llvm-svn: 57672
2008-10-17 06:11:48 +00:00
ca0546facc
Fun x86 encoding tricks: when adding an immediate value of 128,
...
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
llvm-svn: 57663
2008-10-17 01:33:43 +00:00
a39b0a1f05
Define patterns for shld and shrd that match immediate
...
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
llvm-svn: 57662
2008-10-17 01:23:35 +00:00
e33afda4fa
Trim #includes.
...
llvm-svn: 57649
2008-10-16 20:18:31 +00:00
ba88d86a65
fix typo noticed by sdt
...
llvm-svn: 57644
2008-10-16 17:02:50 +00:00
dc84511146
Fix warnings about mb/me being potentially used
...
uninitialized in these functions with gcc-4.3.
llvm-svn: 57635
2008-10-16 13:02:33 +00:00
305fb0a7ba
add some notes
...
llvm-svn: 57631
2008-10-16 07:04:06 +00:00
29628cc5da
add some notes and a file to collect unimplemented features in the
...
x86 backend. These will all be answered with "patches welcome", so
a PR doesn't help drive them along.
llvm-svn: 57630
2008-10-16 06:46:12 +00:00
122c9b1b22
mark some targets as experimental. Andrew, if you think that Alpha is
...
basically working, feel free to remove the tag. The other targets have
really basic things that break them.
llvm-svn: 57628
2008-10-16 06:16:50 +00:00
33332bce17
Const-ify several TargetInstrInfo methods.
...
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
4a87660127
Remove an unused variable.
...
llvm-svn: 57621
2008-10-16 01:47:47 +00:00
6bae5268a7
Fix the predicate for memop64 to be a regular load, not just
...
an unindexed load.
llvm-svn: 57612
2008-10-16 00:03:00 +00:00
9b83197b76
move PR1941 here.
...
llvm-svn: 57586
2008-10-15 16:33:52 +00:00
6d275fd6e1
move PR1604 here.
...
llvm-svn: 57582
2008-10-15 16:06:03 +00:00
843dacc937
move PR1488 into this file.
...
llvm-svn: 57579
2008-10-15 16:02:15 +00:00
29ad439782
Now that predicates can be composed, simplify several of
...
the predicates by extending simple predicates to create
more complex predicates instead of duplicating the logic
for the simple predicates.
This doesn't reduce much redundancy in DAGISelEmitter.cpp's
generated source yet; that will require improvements to
DAGISelEmitter.cpp's instruction sorting, to make it more
effectively group nodes with similar predicates together.
llvm-svn: 57565
2008-10-15 06:50:19 +00:00
117792afec
add a note
...
llvm-svn: 57557
2008-10-15 05:53:25 +00:00
ddb17ce4be
add support for folding immediates into stores when they
...
are due to argument passing in calls. This is significant because
it hits all immediate arguments to calls on x86-32.
llvm-svn: 57556
2008-10-15 05:38:32 +00:00
3ba293564a
fold immediates into stores in simple cases, this produces diffs like
...
this:
- movl $0, %eax
- movl %eax, _yy_n_chars
+ movl $0, _yy_n_chars
llvm-svn: 57555
2008-10-15 05:30:52 +00:00
e388725aef
fold compare of null pointer into compare with 0.
...
llvm-svn: 57553
2008-10-15 05:18:04 +00:00
a0f9d4972f
Some minor cleanups:
...
1. Compute action in X86SelectSelect based on MVT instead of type.
2. Use TLI.getValueType(..) instead of MVT::getVT(..) because the former
handles pointers and the later doesn't.
3. Don't pass TLI into isTypeLegal, since it already has access to it as
an ivar.
#2 gives fast isel some minor new functionality: handling load/stores of
pointers.
llvm-svn: 57552
2008-10-15 05:07:36 +00:00
74e012839d
Use switch on VT instead of Type* comparisons.
...
llvm-svn: 57551
2008-10-15 04:32:45 +00:00
dc1c380f23
Use X86FastEmitCompare for FCMP_OEQ and FCMP_UNE: it doesn't
...
change the generated code, but makes the code simpler.
llvm-svn: 57550
2008-10-15 04:29:23 +00:00
d46b9510b6
refactor compare emission out into a new X86FastEmitCompare method,
...
which makes it easy to share the compare/imm folding logic with 'setcc'.
This shaves a bunch of instructions off the common select case, which
happens a lot in llvm-gcc.
llvm-svn: 57549
2008-10-15 04:26:38 +00:00
88f4754f8f
Fold immediates into compares when possible, producing "cmp $4, %eax" instead of
...
loading 4 into a register and then doing the compare.
llvm-svn: 57548
2008-10-15 04:13:29 +00:00
47bef25c01
more minor refactoring of X86SelectBranch, no functionality change.
...
llvm-svn: 57547
2008-10-15 04:02:26 +00:00
0ce717ac6b
factor buildmi calls in X86SelectBranch
...
llvm-svn: 57546
2008-10-15 03:58:05 +00:00
f32ce221e4
factor some more BuildMI's in X86SelectCmp
...
llvm-svn: 57545
2008-10-15 03:52:54 +00:00
a3596db462
factor some BuildMI calls, no functionality change.
...
llvm-svn: 57544
2008-10-15 03:47:17 +00:00
3b0f5e4d61
- Add target lowering hooks that specify which setcc conditions are illegal,
...
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
llvm-svn: 57542
2008-10-15 02:05:31 +00:00
e7ced74558
FastISel support for exception-handling constructs.
...
- Move the EH landing-pad code and adjust it so that it works
with FastISel as well as with SDISel.
- Add FastISel support for @llvm.eh.exception and
@llvm.eh.selector.
llvm-svn: 57539
2008-10-14 23:54:11 +00:00
28106756af
Accept -march=i586, because gcc does (a synonym
...
for pentium). Fixes
gcc.target/i386/20000720-1.c
gcc.target/i386/pr26826.c
llvm-svn: 57528
2008-10-14 22:06:33 +00:00
07d53b1d33
Rename LoadX to LoadExt.
...
llvm-svn: 57526
2008-10-14 21:26:46 +00:00
b7c01f5f48
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
...
llvm-svn: 57524
2008-10-14 20:36:24 +00:00
9c4b7d5c4f
Fix command-line option printing to print two spaces where needed,
...
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
llvm-svn: 57521
2008-10-14 20:25:08 +00:00
c36231b95e
Fix indentation.
...
llvm-svn: 57508
2008-10-14 17:15:39 +00:00
56b6885104
When doing the very-late shift-and address-mode optimization,
...
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.
If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.
This fixes PR2849.
llvm-svn: 57465
2008-10-13 20:52:04 +00:00
46a9c01fff
Update size of inst correctly with segment override.
...
llvm-svn: 57414
2008-10-12 10:30:11 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
23ee981e8e
Fix comment typo.
...
llvm-svn: 57381
2008-10-11 19:34:24 +00:00
2589777f3f
Add ability to override segment (mostly for code emitter purposes).
...
llvm-svn: 57380
2008-10-11 19:09:15 +00:00
05b54c2af4
Fix SSE4.1 roundss, roundsd. While the instructions have
...
the same pattern as roundpd/roundps, the Intel compiler
builtins do not: rounds* has an extra operand. Fixes
gcc.target/i386/sse4_1-rounds[sd]-[1234].c
llvm-svn: 57370
2008-10-10 23:51:03 +00:00
58deb69040
Fix a thinko and unbreak sparc default CC
...
llvm-svn: 57368
2008-10-10 21:47:37 +00:00
f8a4a0e959
Extend set of return registers on sparc until someone will implement MRV support there. At least, this will allow libgcc compile, however we are not ABI-compatible with stuff compiled with native gcc.
...
llvm-svn: 57364
2008-10-10 20:30:14 +00:00
b80b485264
Ignore extra 'r' modifier for now
...
llvm-svn: 57363
2008-10-10 20:29:50 +00:00
76baad1ffc
Use expand for smul_lohi for now
...
llvm-svn: 57362
2008-10-10 20:29:31 +00:00
281cf247a5
Add rudimentary support for 'r' register operand
...
llvm-svn: 57359
2008-10-10 20:28:10 +00:00
b8736566c2
Cleanup
...
llvm-svn: 57358
2008-10-10 20:27:31 +00:00
3db2173021
Add rudimentary asmprinter support for printing inline asm operands for sparc.
...
llvm-svn: 57346
2008-10-10 10:15:03 +00:00
9aaaa4035e
Add dummy 'm' inline asm constraint handler for Sparc. I'm not sure, whether it is correct, however :)
...
llvm-svn: 57345
2008-10-10 10:14:47 +00:00
1f9487b916
Cleanup
...
llvm-svn: 57344
2008-10-10 10:14:15 +00:00
4f0bd68cfe
Add a "loses information" return value to APFloat::convert
...
and APFloat::convertToInteger. Restore return value to
IEEE754. Adjust all users accordingly.
llvm-svn: 57329
2008-10-09 23:00:39 +00:00
54306fe499
Rename APFloat::convertToAPInt to bitcastToAPInt to
...
make it clearer what the function does. No functional
change.
llvm-svn: 57325
2008-10-09 18:53:47 +00:00
1a84f86271
get CodeGen/Alpha/mul128.ll to work.
...
llvm-svn: 57318
2008-10-09 04:50:56 +00:00
66e08292aa
(re)Put const weak strings in appropriate section on Darwin.
...
g++dg/abi/key2.C
llvm-svn: 57309
2008-10-08 21:49:47 +00:00
d83529e8c4
Comment to be explicit that the enumeration values for CondCodes matter.
...
llvm-svn: 57295
2008-10-08 16:24:35 +00:00
32052e8272
Use template to distinguish between function variants.
...
GCC 4.4.0 gives an error on the "int" declaration for example
saying that it has already been declared (using the "short"
one). Using templates here allow the compiler to distinguish
between the function to choose.
Also, "llvm/Support/DataTypes.h" was not included, leading to
error messages about not knowing "uint32_t" for example.
Patch by Samuel Tardieu.
llvm-svn: 57292
2008-10-08 07:44:52 +00:00
26ff6f9c54
Add <cstdio> include where needed by gcc-4.4.
...
Patch by Samuel Tardieu.
llvm-svn: 57291
2008-10-08 07:23:46 +00:00
b3ba449cfb
Add MBB successors and physreg Uses in the same order that
...
SDISel typically adds them in. This makes it a little easier
to compare FastISel output with SDISel output.
llvm-svn: 57266
2008-10-07 22:10:33 +00:00
d3917157d5
Instead of emitting an implicit use for the super-register of
...
X86::CL that was used, emit an EXTRACT_SUBREG from the CL
super-register to CL. This more precisely describes how the
CL register is being used.
llvm-svn: 57264
2008-10-07 21:50:36 +00:00
f311fe142c
Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
...
llvm-svn: 57262
2008-10-07 21:08:09 +00:00
b53acd8caa
need ARM.h for ARMCC definition
...
llvm-svn: 57261
2008-10-07 21:01:51 +00:00
1d338fc6a4
Add an option to enable StrongPHIElimination, for ease of testing.
...
llvm-svn: 57259
2008-10-07 20:22:28 +00:00
c084e84028
Encode the conditional execution predicate when JITing.
...
llvm-svn: 57258
2008-10-07 19:05:35 +00:00
422ef88f31
Model hardwired inputs & outputs of x86 8-bit divides correctly.
...
Fixes local RA miscompilation of gcc.c-torture/execute/20020904-1.c -O0.
llvm-svn: 57257
2008-10-07 18:54:28 +00:00
2fb5c3938b
Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
...
llvm-svn: 57252
2008-10-07 17:42:09 +00:00
1d54d4f375
Fix Opcode values of CMP and CMN
...
llvm-svn: 57251
2008-10-07 17:40:46 +00:00
1699ad9030
Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
...
llvm-svn: 57246
2008-10-07 16:14:11 +00:00
64861a7181
Note that ADDC and company don't actually expand yet (missing in legalize
...
llvm-svn: 57226
2008-10-07 02:10:26 +00:00
94d14f2d45
Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.
...
llvm-svn: 57210
2008-10-06 21:13:08 +00:00
c0f3b52e65
It is possible that all functions in one module are not being
...
optimized for size. Set OptForSize for each function separately.
llvm-svn: 57182
2008-10-06 18:03:39 +00:00
ab379c905b
Remove unncessary isDeclaration() checks.
...
llvm-svn: 57179
2008-10-06 17:30:07 +00:00
37e560cde1
Emit type-correct constant null. Also fix a typo.
...
Patch by Robert G. Jakabosky!
llvm-svn: 57110
2008-10-05 15:07:06 +00:00
d2aded08ac
Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
...
llvm-svn: 57106
2008-10-05 08:53:29 +00:00
f9325e5f67
this case is matched now.
...
llvm-svn: 57096
2008-10-05 02:16:12 +00:00
b52ef06c8c
Revert r56675 - it breaks unwinding runtime everywhere.
...
llvm-svn: 57048
2008-10-04 11:09:36 +00:00
8c36a1c09c
Make atomic Swap work, 64-bit on x86-32.
...
Make it all work in non-pic mode.
llvm-svn: 57034
2008-10-03 22:25:52 +00:00
5d60c1ebb1
Pass MemOperand through for 64-bit atomics on 32-bit,
...
incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
llvm-svn: 57027
2008-10-03 19:41:08 +00:00
2c836cf187
Avoid creating two TargetLowering objects for each target.
...
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
llvm-svn: 57016
2008-10-03 16:55:19 +00:00
eae96ce3ec
Remove an unused field.
...
llvm-svn: 57014
2008-10-03 16:17:33 +00:00
332ad5e016
Indexing off by one resulted in errant encoding of source register for
...
reg->reg moves.
llvm-svn: 57011
2008-10-03 15:53:56 +00:00
af929abc01
NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub
...
for global relocations that do need them (libc calls, for example).
llvm-svn: 57010
2008-10-03 15:52:42 +00:00
0d1e9a8e04
Switch the MachineOperand accessors back to the short names like
...
isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
b01a9c94d4
Fix X86FastISel to handle dynamic allocas that have avoided
...
getting inserted into the ValueMap. This avoids infinite
recursion in some rare cases.
llvm-svn: 56989
2008-10-03 01:27:49 +00:00
1ab1d31f7a
Optimize conditional branches in X86FastISel. This replaces
...
sequences like this:
sete %al
testb %al, %al
jne LBB11_1
with this:
je LBB11_1
llvm-svn: 56969
2008-10-02 22:15:21 +00:00
867d549fce
Handle some 64-bit atomics on x86-32, some of the time.
...
llvm-svn: 56963
2008-10-02 18:53:47 +00:00
b158fd751c
Work around an interaction between fast-isel and regalloc=local. The
...
local register allocator's physreg liveness doesn't recognize subregs,
so it doesn't know that defs of %ecx that are immediately followed by
uses of %cl aren't dead. This comes up due to the way fast-isel emits
shift instructions.
This is a temporary workaround. Arguably, local regalloc should
handle subreg references correctly. On the other hand, perhaps
fast-isel should use INSERT_SUBREG instead of just assigning to the
most convenient super-register of %cl when lowering shifts.
This fixes MultiSource/Benchmarks/MallocBench/espresso,
MultiSource/Applications/hexxagon, and others, under -fast.
llvm-svn: 56947
2008-10-02 14:56:12 +00:00
b04e6edba9
"The original bug was a complaint that _mm_srli_si128 mis-compiled when passed
...
a constant vector ("{0x123, 0x456}" syntax). The fix is to simplify the
_mm_srli_si128 macro, and move the "* 8" from the macro into the compiler
back-end. I can't change the existing __builtins because so many people are
using them :-(."
Patch by Stuart Hastings!
llvm-svn: 56944
2008-10-02 05:56:52 +00:00
1b76f2c40b
Remove OptimizeForSize global. Use function attribute optsize.
...
llvm-svn: 56937
2008-10-01 23:18:38 +00:00
6388dde98e
Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms.
...
This allows the 64-bit forms to use+def RSP instead of ESP. This
doesn't fix any real bugs today, but it is more precise and it
makes the debug dumps on x86-64 look more consistent.
Also, add some comments describing the CALL instructions' physreg
operand uses and defs.
llvm-svn: 56925
2008-10-01 18:28:06 +00:00
3dc0a3bce3
Fix typo s/ther/there/
...
llvm-svn: 56924
2008-10-01 18:16:49 +00:00
bb3c5019f8
Mark CALL instructions as having a Use of ESP/RSP.
...
llvm-svn: 56911
2008-10-01 04:14:30 +00:00
68f12ee567
Implement the -fno-builtin option in the front-end, not in the back-end.
...
llvm-svn: 56900
2008-10-01 00:59:58 +00:00
1782584f56
Just don't transform this memset into "bzero" if no-builtin is specified.
...
llvm-svn: 56888
2008-09-30 22:05:33 +00:00
bd09262e97
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
...
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
llvm-svn: 56885
2008-09-30 21:22:07 +00:00
86aa16a69a
Optimize SelectionDAG's AssignTopologicalOrder even further.
...
Completely eliminate the TopOrder std::vector. Instead, sort
the AllNodes list in place. This also eliminates the need to
call AllNodes.size(), a linear-time operation, before
performing the sort.
Also, eliminate the Sources temporary std::vector, since it
essentially duplicates the sorted result as it is being
built.
This also changes the direction of the topological sort
from bottom-up to top-down. The AllNodes list starts out in
roughly top-down order, so this reduces the amount of
reordering needed. Top-down is also more convenient for
Legalize, and ISel needed only minor adjustments.
llvm-svn: 56867
2008-09-30 18:30:35 +00:00
8392f0c75d
Fix X86FastISel's output for x86-32 PIC constant pool addresses.
...
llvm-svn: 56829
2008-09-30 01:21:32 +00:00
6ebe734ca6
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
...
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.
llvm-svn: 56825
2008-09-30 00:58:23 +00:00
5033136825
Disable all x87 usage, including f32 and f64 when the subtarget
...
doesn't have SSE(2), with X86FastISel.
llvm-svn: 56823
2008-09-30 00:48:39 +00:00
f61a84ec43
Remove misuse of ReplaceNodeResults for atomics with
...
valid types. No functional change.
llvm-svn: 56808
2008-09-29 22:25:26 +00:00
c02dbf451e
Fix an over-pessimization about GlobalVariable addresses in X86FastISel.
...
llvm-svn: 56802
2008-09-29 21:13:15 +00:00
82237f2f42
Fix PR2835. Do not change the width of a volatile load.
...
llvm-svn: 56792
2008-09-29 17:26:18 +00:00
08d91178e9
Rename isWeakForLinker to mayBeOverridden. Use it
...
instead of hasWeakLinkage in a bunch of optimization
passes.
llvm-svn: 56782
2008-09-29 11:25:42 +00:00
3774b2f292
Re-apply 56683 with fixes.
...
llvm-svn: 56748
2008-09-27 01:56:22 +00:00
1d5e766016
Unbreak build.
...
llvm-svn: 56727
2008-09-27 00:22:09 +00:00
9eb525d4f9
Implement function notes as function attributes.
...
llvm-svn: 56716
2008-09-26 23:51:19 +00:00
7d6fa97567
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
...
llvm-svn: 56711
2008-09-26 23:41:32 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
6e0548336a
Rename ConstantSDNode's getSignExtended to getSExtValue, for
...
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
llvm-svn: 56700
2008-09-26 21:54:37 +00:00
7e922aa35d
Mark lea fi# as being really rematerializable.
...
llvm-svn: 56698
2008-09-26 21:30:20 +00:00
30f5494efb
unpckhps requires sse1, punpckhdq requires sse2.
...
llvm-svn: 56697
2008-09-26 21:26:30 +00:00
2564b900ce
Fix X86FastISel's address folding to check displacement
...
values for overflow.
llvm-svn: 56686
2008-09-26 20:04:15 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
...
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
9e3f7dbeda
CMake: Builds all examples. Corrected name of CBackend target.
...
llvm-svn: 56682
2008-09-26 19:48:03 +00:00
0e32a2c935
Add "inreg" field to CallSDNode (doesn't increase
...
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
llvm-svn: 56677
2008-09-26 19:31:26 +00:00
007a6bb9b9
Factor out the code for determining when symblic addresses
...
require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.
llvm-svn: 56676
2008-09-26 19:15:30 +00:00
994dd0bbec
Avoid spilling EBP / RBP twice in the prologue.
...
llvm-svn: 56675
2008-09-26 19:14:21 +00:00
001ffdd36b
X86 address displacement field must be interpreted as a 32-bit value.
...
llvm-svn: 56665
2008-09-26 16:58:16 +00:00
cdc95498f5
CMake: Builds all targets.
...
llvm-svn: 56641
2008-09-26 04:40:32 +00:00
839105d254
Disable support for x86_f80 in X86FastISel. Supporting it would
...
require more work.
llvm-svn: 56637
2008-09-26 01:39:32 +00:00
374d7f2b16
If we have a function with an unreachable statement such that the ending debug
...
information is in an unreachable block, then it's possible that the high/low pc
values won't be set for the dwarf information. E.g., this function:
void abort(void) __attribute__((__noreturn__));
void dead_beef(void) __attribute__ ((noreturn));
int *b;
void dead_beef(void) {
*b=0xdeadbeef;
abort();
}
has a call to "@llvm.dbg.region.end" only in the unreachable block:
define void @dead_beef() noreturn nounwind {
entry:
call void @llvm.dbg.func.start(...)
call void @llvm.dbg.stoppoint(...)
...
call void @abort( ) noreturn nounwind
unreachable
return: ; No predecessors!
call void @llvm.dbg.stoppoint(...)
call void @llvm.dbg.region.end(...)
ret void
}
The dwarf information emitted is something like:
0x00000084: TAG_subprogram [5]
AT_name( "dead_beef" )
AT_external( 0x01 )
AT_prototyped( 0x01 )
AT_decl_file( 0x01 )
AT_decl_line( 0x08 )
Note that this is *not* the best fix for this problem, but a band-aid for an
gaping wound. This code needs to be changed when we revamp our debugging
information.
llvm-svn: 56628
2008-09-26 00:28:12 +00:00
9dbe45c000
Prefer movlhps over punpcklqdq, etc. in more cases.
...
llvm-svn: 56627
2008-09-25 23:35:16 +00:00
0c1b884df1
Fix a bug in which address displacements were being added to the
...
load from the stub, instead of the result of the load from the stub.
llvm-svn: 56626
2008-09-25 23:34:02 +00:00
4c758ea3e0
Large mechanical patch.
...
s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g
This sets the stage
- to implement function notes as function attributes and
- to distinguish between function attributes and return value attributes.
This requires corresponding changes in llvm-gcc and clang.
llvm-svn: 56622
2008-09-25 21:00:45 +00:00
87001fd6fd
Reapply 56585:56589 with proper fix for some gcc versions
...
llvm-svn: 56621
2008-09-25 21:00:33 +00:00
74c9ed91b0
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
...
llvm-svn: 56620
2008-09-25 20:50:48 +00:00
c50ada2f56
Accept 'inreg' attribute on x86 functions as
...
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0). Update documentation
to reflect reality.
llvm-svn: 56619
2008-09-25 20:47:45 +00:00
3691d507c4
PIC support in X86FastISel.
...
llvm-svn: 56608
2008-09-25 15:24:26 +00:00
84301390ae
Temporarily backing out 56585:56589 to unbreak the build.
...
llvm-svn: 56607
2008-09-25 07:38:08 +00:00
7b5a6afb44
pmovsxbq etc. requires sse4.1.
...
llvm-svn: 56600
2008-09-25 00:49:51 +00:00
f8ead16b50
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
...
llvm-svn: 56594
2008-09-24 23:27:55 +00:00
4751549f9b
X86ISD::VZEXT_LOAD should produce and fold a chain.
...
llvm-svn: 56593
2008-09-24 23:26:36 +00:00
3097c10347
Minor cleanup
...
llvm-svn: 56588
2008-09-24 22:22:54 +00:00
a9163feefe
Get rid of virtual inheritance for ARM TAI
...
llvm-svn: 56587
2008-09-24 22:22:27 +00:00
237f087eb9
Get rid of virtual inheritance for PPC TAI
...
llvm-svn: 56586
2008-09-24 22:22:03 +00:00
77aa975bdd
Use crazy template-based inheritance instead of virtual one.
...
llvm-svn: 56585
2008-09-24 22:21:39 +00:00
8e7b93938d
Get rid of ReadOnlySection duplicate
...
llvm-svn: 56582
2008-09-24 22:20:27 +00:00
91a6705839
Use named sections, where they should be
...
llvm-svn: 56581
2008-09-24 22:19:13 +00:00
5906234c1d
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
...
llvm-svn: 56580
2008-09-24 22:18:54 +00:00
41573b2131
Cleanup
...
llvm-svn: 56578
2008-09-24 22:17:27 +00:00
22db30548d
Get rid of duplicate char*/Section* stuff for TLS sections
...
llvm-svn: 56577
2008-09-24 22:17:06 +00:00
1f365bbf55
Cleanup, no functionality change
...
llvm-svn: 56576
2008-09-24 22:16:33 +00:00
7497762606
Get rid of duplicate char*/Section* DataSection
...
llvm-svn: 56575
2008-09-24 22:16:16 +00:00
f8dc8aac3c
Get rid of duplicate char*/Section* TextSection
...
llvm-svn: 56574
2008-09-24 22:15:21 +00:00
076e905b94
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
...
llvm-svn: 56573
2008-09-24 22:14:23 +00:00
69ff51baa0
Drop obsolete hook and change all usage to new interface
...
llvm-svn: 56572
2008-09-24 22:13:07 +00:00
8ac1127ed6
SPU section handling is really huge mess. Replace remaining TAI calls for sections with explicit names in order not to block existing backends during section handling migration. SPU folks! Please consider using new section handling facility someday.
...
llvm-svn: 56570
2008-09-24 22:11:42 +00:00
69721aa85c
Remove dead code for PIC16 (preparation to switch to new section handling stuff)
...
llvm-svn: 56569
2008-09-24 22:11:26 +00:00
ffecb087a3
XMM6-XMM15 are callee-saved on Win64. Patch by Nicolas Capens!
...
llvm-svn: 56568
2008-09-24 22:03:04 +00:00
6402c7236f
s/ParamAttrsWithIndex/FnAttributeWithIndex/g
...
llvm-svn: 56535
2008-09-24 00:55:02 +00:00
e15607b7bb
Put FN_NOTE_AlwaysInline and others in FnAttr namespace.
...
llvm-svn: 56527
2008-09-24 00:06:15 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
e87abd26ba
Move FN_NOTE_AlwaysInline and other out of ParamAttrs namespace.
...
Do not check isDeclaration() in hasNote(). It is clients' responsibility.
llvm-svn: 56524
2008-09-23 23:52:03 +00:00
ba3fa6c6e1
s/ParameterAttributes/Attributes/g
...
llvm-svn: 56513
2008-09-23 23:03:40 +00:00
82fed6702b
Use parameter attribute store (soon to be renamed) for
...
Function Notes also. Function notes are stored at index ~0.
llvm-svn: 56511
2008-09-23 22:35:17 +00:00
918fe08a56
Arrange for FastISel code to have access to the MachineModuleInfo
...
object. This will be needed to support debug info.
llvm-svn: 56508
2008-09-23 21:53:34 +00:00
ed1cf1a8f1
Fix these enums' starting values to reflect the way that
...
instruction opcodes are now numbered. No functionality change.
llvm-svn: 56497
2008-09-23 18:42:32 +00:00
e64c9944f6
Delete an unused function.
...
llvm-svn: 56495
2008-09-23 18:26:47 +00:00
2430073657
Move the code for initializing the global base reg out of
...
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.
llvm-svn: 56494
2008-09-23 18:22:58 +00:00
bdb215d338
Fix indendation.
...
llvm-svn: 56486
2008-09-23 08:54:41 +00:00
9e9426cb82
Support x86 specific inline asm modifier 'J'.
...
llvm-svn: 56483
2008-09-22 23:57:37 +00:00
329fe728b5
Add hasNote() to check note associated with a function.
...
llvm-svn: 56477
2008-09-22 22:32:29 +00:00
962c2cf17a
Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
...
llvm-svn: 56475
2008-09-22 22:21:38 +00:00
7a74e71489
Make log, log2, log10, exp, exp2 use Expand by
...
default.
llvm-svn: 56471
2008-09-22 21:57:32 +00:00
168f8f3916
Mark several codegen passes as preserving all analysis.
...
llvm-svn: 56469
2008-09-22 20:58:04 +00:00
8807bddf08
CMake build system: support for parallel builds.
...
llvm-svn: 56453
2008-09-22 18:21:51 +00:00
796a271c5f
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
...
llvm-svn: 56436
2008-09-22 14:50:07 +00:00
a229b3c9a7
Initial support for the CMake build system.
...
llvm-svn: 56419
2008-09-22 01:08:49 +00:00
f1280cf744
Fold immediates into X86 shifts with fast isel. This generates:
...
sarl $3, %ecx
instead of:
movl $3, %ecx
sarl %cl, %edx
This shrinks fast isel 176.gcc by about 2000 instructions (.3%)
llvm-svn: 56413
2008-09-21 21:44:29 +00:00
dfc19e6c01
Instead of building a list and sorting it just to find a maximum element,
...
compute the maximum element directly.
llvm-svn: 56411
2008-09-21 21:01:49 +00:00
9a8eb0d534
add a note
...
llvm-svn: 56391
2008-09-20 19:17:53 +00:00
4730522235
No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
...
llvm-svn: 56378
2008-09-20 00:13:45 +00:00
9d917beba6
80 column violation.
...
llvm-svn: 56377
2008-09-20 00:13:08 +00:00
098786e9f7
Fix a FastISel GlobalVariable CSE bug.
...
llvm-svn: 56376
2008-09-19 23:42:04 +00:00
9801ba451a
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
...
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
llvm-svn: 56371
2008-09-19 22:16:54 +00:00
6e005fdc8d
Address-mode folding for X86FastISel. It's pretty basic, but it
...
catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.
llvm-svn: 56320
2008-09-18 23:23:44 +00:00
e91edeb61c
Simplify this code. The FastISel class has its own TD member.
...
llvm-svn: 56311
2008-09-18 18:26:43 +00:00
933b392f65
Duh. Default to ARMCC::AL (always).
...
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
5e3ac187d9
Clean up.
...
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
bc0d0eccf3
Cosmetic.
...
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
af13bf1ebd
FastISel: For calls, prefer using the callee's address as a constant
...
over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.
This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.
llvm-svn: 56292
2008-09-17 21:18:49 +00:00
7848cfcd77
Fix addrmode1 instruction encodings; fix bx_ret encoding.
...
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
937569afe3
Specify instruction encoding using range list to avoid endianess issues.
...
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
173aa8602d
Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
...
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.
llvm-svn: 56270
2008-09-17 01:39:10 +00:00
95e1af217f
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
...
function with appropriate parameters. This allows us to support blocks on PPC.
llvm-svn: 56267
2008-09-17 00:30:57 +00:00
24c79f28b1
Reverting r56249. On further investigation, this functionality isn't needed.
...
Apologies for the thrashing.
llvm-svn: 56251
2008-09-16 21:48:12 +00:00
8bc392fb1d
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
...
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
llvm-svn: 56249
2008-09-16 21:12:30 +00:00
233785daae
Fixed Bug 2751
...
http://llvm.org/bugs/show_bug.cgi?id=2751
Abicall was enabled even when static code model was provided
in the command line.
The correct behavior is to disable abicall when static is
specified.
llvm-svn: 56228
2008-09-15 21:06:55 +00:00
38453eebdc
Remove isImm(), isReg(), and friends, in favor of
...
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
2008-09-13 17:58:21 +00:00
a5804effed
Fix random abort.
...
llvm-svn: 56184
2008-09-13 01:55:59 +00:00
d3fe174c53
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
...
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
llvm-svn: 56183
2008-09-13 01:54:27 +00:00
380482ac46
Typo.
...
llvm-svn: 56182
2008-09-13 01:44:01 +00:00
ba28161103
Rely on instruction format to determine so_reg operand for now.
...
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
...
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
db6571a2c7
Accidentially flipped the condition.
...
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
25a39094f8
Add debug dumps.
...
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
...
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
d1424c4eca
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
...
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
33fa89c6fb
Rewrite address mode 1 code emission routines.
...
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
a7cd7bc353
udpate header comment: s/VP/VFP/
...
llvm-svn: 56126
2008-09-11 21:41:29 +00:00
dd45bc25ac
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
...
llvm-svn: 56119
2008-09-11 20:28:43 +00:00
453564bfba
Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel.
...
llvm-svn: 56117
2008-09-11 19:44:55 +00:00
58d084c05b
The version of AtomicSDNode::AtomicSDNode used (only) for
...
cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional. Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.
From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out. I
cannot test on that platform.
llvm-svn: 56091
2008-09-11 03:12:59 +00:00
41baf8b22a
If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on
...
X86-64 in fast isel.
llvm-svn: 56088
2008-09-11 02:41:37 +00:00
e5ca04e70d
Succumb utterly to compatibility and implement
...
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
llvm-svn: 56087
2008-09-11 02:15:03 +00:00
bf646f2986
X86FastISel support for double->float and float->double casts.
...
llvm-svn: 56070
2008-09-10 21:02:08 +00:00
39d82f902a
Add X86FastISel support for static allocas, and refences
...
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
llvm-svn: 56066
2008-09-10 20:11:02 +00:00
710c3cf36a
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
...
llvm-svn: 56061
2008-09-10 18:25:29 +00:00
4cc893bab6
Handle new intrinsics with vector arguments.
...
Patch by Paul Redmond.
llvm-svn: 56059
2008-09-10 17:31:40 +00:00
6d6a65310b
Fix name.
...
llvm-svn: 56055
2008-09-10 13:22:10 +00:00
83e45acc25
Add trampoline support for the new FastCC calling
...
convention (not related to recent Ada testsuite
failures).
llvm-svn: 56054
2008-09-10 13:11:09 +00:00
536c399579
Turn off the new FastCC for the moment. It causes
...
a slew of Ada testsuite failures on x86-32 linux.
Seems to be related to the use of float.
llvm-svn: 56053
2008-09-10 13:09:24 +00:00
abb1e7770b
Move the uglier parts of deciding not to emit a
...
UsedDirective for some symbols in llvm.used into
Darwin-specific code. I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.
llvm-svn: 56024
2008-09-09 22:29:13 +00:00
1a1140429e
Make safer variant of alias resolution routine to be default
...
llvm-svn: 56005
2008-09-09 20:05:04 +00:00
4fcccd8d66
Mark IMPLICIT_DEF as being rematerializable and cheap-as-a-move.
...
It's already special-cased and treated as rematerializable within
LiveIntervals; this allows it to be handled by other passes
such as TwoAddressInstrctionPass.
llvm-svn: 55999
2008-09-09 18:25:28 +00:00
6acb2219b6
Replace explicit pointer-size constants to TargetData query.
...
No functionality change.
llvm-svn: 55996
2008-09-09 18:22:57 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
...
llvm-svn: 55975
2008-09-09 01:26:59 +00:00
f080225490
Fix logic for not emitting no-dead-strip for some
...
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
llvm-svn: 55973
2008-09-09 01:21:22 +00:00
177eda0505
Reapply 55901: Drop unused variable
...
llvm-svn: 55957
2008-09-08 21:13:33 +00:00
524820fef7
Reapply 55900: We do support EH on x86-64!
...
llvm-svn: 55956
2008-09-08 21:13:08 +00:00
2fd24e7713
Reapply 55899: First draft of EH support on x86/64-linux
...
Now with fix, which prevents subtle codegen bug to trigger on darwin.
No fix for bug though, it's still there.
llvm-svn: 55955
2008-09-08 21:12:47 +00:00
4112634ca6
Reapply blindly reverted 55898: Implement FRAME_TO_ARGS_OFFSET for x86-64
...
llvm-svn: 55954
2008-09-08 21:12:11 +00:00
3871441861
Reverting r55898 as well. This wasn't reverted in the original revert...
...
llvm-svn: 55938
2008-09-08 19:42:32 +00:00
6fe5fe4209
Accidental commit of partial 'stack canaries' code
...
llvm-svn: 55937
2008-09-08 18:12:00 +00:00
99b83712f3
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
llvm-svn: 55928
2008-09-08 17:59:12 +00:00
d172048b59
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
...
llvm-svn: 55925
2008-09-08 17:15:42 +00:00
fd18d630bc
i128 and f80 are implemented for x86-64 now.
...
llvm-svn: 55920
2008-09-08 16:42:56 +00:00
8f658bac2f
Fix copy+pastos in comments.
...
llvm-svn: 55918
2008-09-08 16:31:35 +00:00
4d5b5fe812
Delete an unused variable.
...
llvm-svn: 55915
2008-09-08 16:28:17 +00:00
b55688d27d
Drop unused variable
...
llvm-svn: 55901
2008-09-08 14:22:38 +00:00
0316b797ea
We do support EH on x86-64!
...
llvm-svn: 55900
2008-09-08 14:22:16 +00:00
82b9540046
First draft of EH support on x86/64-linux
...
llvm-svn: 55899
2008-09-08 14:21:53 +00:00
cb0655d626
Implement FRAME_TO_ARGS_OFFSET for x86-64
...
llvm-svn: 55898
2008-09-08 14:21:10 +00:00
6500d1711a
Add support to extend call operands when needed. Enable x86 fastisel call support.
...
llvm-svn: 55891
2008-09-08 06:35:17 +00:00
6c8f55c841
Initial fastisel call support for C, Fast, and X86_FastCall calling conventions. It's meant to handle "simple" calls, i.e. no byval, structret, etc. It doesn't support multi-result returns either.
...
Not yet turned on, it needs to support sext / zext of arguments and result.
llvm-svn: 55882
2008-09-07 09:09:33 +00:00
6f343bd543
Some code clean up.
...
llvm-svn: 55881
2008-09-07 09:07:23 +00:00
b928669409
Handle x86 truncate to i8 with target hook for now.
...
llvm-svn: 55877
2008-09-07 08:47:42 +00:00
d41c7160d0
Fix constant pool loads, and remove broken versions of addConstantPoolReference.
...
llvm-svn: 55868
2008-09-06 01:11:01 +00:00
9519fb3f50
Fix the X86 addConstantPoolReference, which had the operands in the wrong order.
...
llvm-svn: 55867
2008-09-06 00:50:00 +00:00
a9c52c8219
Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x
...
i32>. This is a little messy, but it works.
We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.
llvm-svn: 55864
2008-09-05 23:07:03 +00:00
db06a99239
Fix X86FastISel's shift and select code to reject illegal types.
...
llvm-svn: 55857
2008-09-05 21:27:34 +00:00
e556018dc0
Fix the opcodes used by X86FastISel for shifts and conditional moves.
...
llvm-svn: 55855
2008-09-05 21:13:04 +00:00
f5bc7e57bc
Factor out code that emits load and store instructions.
...
llvm-svn: 55854
2008-09-05 21:00:03 +00:00
ffcc884c77
Rename method.
...
llvm-svn: 55853
2008-09-05 20:49:33 +00:00
7d7a26df65
X86FastISel support for shifts and conditional moves.
...
llvm-svn: 55844
2008-09-05 18:30:08 +00:00
4f0d21592a
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
...
llvm-svn: 55840
2008-09-05 17:24:07 +00:00
09faf81b6c
Check a comparion's operand type for legality before
...
expanding its operands.
llvm-svn: 55820
2008-09-05 01:33:56 +00:00
ffd89d40d2
Fix X86FastISel code for comparisons and conditional branches
...
to check the result of getRegForValue before using it, and
to check for illegal operand types.
llvm-svn: 55819
2008-09-05 01:15:35 +00:00
a5753b31be
X86FastISel support for conditional branches.
...
llvm-svn: 55816
2008-09-05 01:06:14 +00:00
50288e3c99
Add initial support for selecting constant materializations that require constant
...
pool loads on X86 in fast isel. This isn't actually used yet.
llvm-svn: 55814
2008-09-05 00:06:23 +00:00
09fdbcf400
X86FastISel support for ICmpInst and FCmpInst.
...
llvm-svn: 55811
2008-09-04 23:26:51 +00:00
6c94b99c62
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
...
llvm-svn: 55807
2008-09-04 22:59:58 +00:00
b9d5e02811
If function notes say optimize for size, then adjust alignment.
...
llvm-svn: 55794
2008-09-04 21:03:41 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
...
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
b8c7ba228f
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
...
llvm-svn: 55777
2008-09-04 16:48:33 +00:00
634412fe35
Clean up uses of TargetLowering::getTargetMachine.
...
llvm-svn: 55769
2008-09-04 15:39:15 +00:00
4f948bd87a
Add a first attempt at implementing stores for X86 fast isel using target hooks.
...
Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
8d8f47d50b
Load from GV stub should be locally CSE'd.
...
llvm-svn: 55763
2008-09-04 06:18:33 +00:00
3152edf474
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
...
llvm-svn: 55756
2008-09-04 01:04:15 +00:00
da2d80688b
Add intrinsics for log, log2, log10, exp, exp2.
...
No functional change (and no FE change to generate them).
llvm-svn: 55753
2008-09-04 00:47:13 +00:00
7bda51f5a4
Create HandlePHINodesInSuccessorBlocksFast, a version of
...
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
llvm-svn: 55746
2008-09-03 23:12:08 +00:00
a41ee2974b
Add X86 target hook to implement load (even from GlobalAddress).
...
llvm-svn: 55693
2008-09-03 06:44:39 +00:00
2175b55dc7
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
...
llvm-svn: 55687
2008-09-03 02:54:11 +00:00
8f23ec96b0
Unbreak fast isel.
...
llvm-svn: 55685
2008-09-03 01:04:47 +00:00
24422d4928
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
...
llvm-svn: 55679
2008-09-03 00:03:49 +00:00
bc69829b22
Fix some bugs in the code sequences for atomics.
...
llvm-svn: 55643
2008-09-02 20:30:23 +00:00
df8cdc3717
Add Mac OS X compatible JIT callback routine.
...
llvm-svn: 55625
2008-09-02 07:49:03 +00:00
3be5b728b1
Revamp ARM JIT.
...
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
34f3a962b0
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
...
llvm-svn: 55623
2008-09-02 06:51:36 +00:00
fa558788e7
Control flow instruction encodings.
...
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
c288cc0572
ldm / stm instruction encodings.
...
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
c37532b24a
AXI2 and AXI3 instruction encodings.
...
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
a282723499
Reorganize instruction formats again; AXI1 encoding.
...
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
169eccc24e
addrmode3 instruction encodings.
...
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
624844b4dd
Reorganize some instruction format definitions. No functionality change.
...
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
cccca875b1
Rest of addrmode2 instruction encodings.
...
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
01fd3f129a
Addr2 word / byte load encodings.
...
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
5b6c931e1f
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
...
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
81d6a38434
fix a bunch of 80-col violations
...
llvm-svn: 55588
2008-08-31 15:37:04 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
...
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
62cf24343c
Expand for ROTR with MVT::i64.
...
Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
a719239719
fix some 80-col violations
...
llvm-svn: 55565
2008-08-30 10:09:02 +00:00
b8d588d89c
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
...
llvm-svn: 55562
2008-08-30 08:54:22 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
...
llvm-svn: 55558
2008-08-30 02:03:58 +00:00
340d264f52
Add ppc partial-word ATOMIC_CMP_SWAP.
...
llvm-svn: 55554
2008-08-30 00:08:53 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
...
llvm-svn: 55553
2008-08-29 23:22:12 +00:00
f93bc7f755
Use static_cast instead of C style cast.
...
llvm-svn: 55552
2008-08-29 23:21:31 +00:00
b3ed09703c
Backing out 55521. Not safe.
...
llvm-svn: 55548
2008-08-29 22:13:21 +00:00
f0a88d6b2a
Add partial word version of ATOMIC_SWAP.
...
llvm-svn: 55546
2008-08-29 18:29:46 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
...
llvm-svn: 55545
2008-08-29 17:45:56 +00:00
44b2138b9a
TableGen'ing instruction encodings.
...
llvm-svn: 55533
2008-08-29 07:42:03 +00:00
c139c221dd
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
...
llvm-svn: 55531
2008-08-29 07:40:52 +00:00
9f717afd68
MVN is addrmode1.
...
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
ee98fa9db2
More refactoring.
...
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
...
llvm-svn: 55521
2008-08-28 23:48:31 +00:00
2d37f19ef2
Refactor ARM instruction format definitions into a separate file. No functionality changes.
...
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
d58f3e36d0
Add a target callback for FastISel.
...
llvm-svn: 55512
2008-08-28 23:21:34 +00:00
95d77f5466
remove tabs, fix > 80 cols
...
llvm-svn: 55511
2008-08-28 23:19:51 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
...
llvm-svn: 55499
2008-08-28 21:04:05 +00:00
26d54b3ef3
Use resize instead of reserve. Reserve doesn't change size().
...
llvm-svn: 55486
2008-08-28 18:32:53 +00:00
a32affb9ba
Implement partial-word binary atomics on ppc.
...
llvm-svn: 55478
2008-08-28 17:53:09 +00:00
97af20f85f
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.
...
llvm-svn: 55466
2008-08-28 07:52:25 +00:00
41be0d4445
Split the ATOMIC NodeType's to include the size, e.g.
...
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
llvm-svn: 55457
2008-08-28 02:44:49 +00:00
76105a4a4f
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
...
SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
7f2777e8d2
Reinstate the x86-64 portion of r55190. When doing extloads into
...
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.
llvm-svn: 55422
2008-08-27 17:33:15 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
...
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
42ccd39689
These assertions should be return false's instead, allowing the client to detect the failure.
...
llvm-svn: 55377
2008-08-26 18:50:40 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
...
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
09f8cef571
If an xmm register is referenced explicitly in an inline asm, make sure to
...
assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
4884f87822
This is done.
...
llvm-svn: 55348
2008-08-26 01:13:44 +00:00
d4eb0521e4
Implement 32 & 64 bit versions of PPC atomic
...
binary primitives.
llvm-svn: 55343
2008-08-25 22:34:37 +00:00
2da2e65d7d
80 col. violations.
...
llvm-svn: 55341
2008-08-25 21:58:43 +00:00
f00f1e50b5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
...
llvm-svn: 55338
2008-08-25 21:27:18 +00:00
765065c982
Remove PPC-specific lowering for atomics; the
...
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
llvm-svn: 55336
2008-08-25 21:09:52 +00:00
166d6cb1fa
It's important for the cmp-and-swap to balance
...
loads and stores but it's even more important for
it to store the right value.:(
llvm-svn: 55319
2008-08-25 18:53:26 +00:00
6cfd3830fb
Nevermind. This broke the bootstrap (?!).
...
llvm-svn: 55318
2008-08-25 18:32:39 +00:00
dd6759aea7
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
...
instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
e414681352
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
...
llvm-svn: 55300
2008-08-25 04:11:42 +00:00
5b836c5f77
Temporarily reverting r55292. It's causing a bootstraping failure:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
2008-08-24 21:45:30 +00:00
8fa17424f7
Move callseq_start above the call address load to allow load to be folded into the call node.
...
llvm-svn: 55292
2008-08-24 19:19:55 +00:00
404cd15fa5
Use additionnal include directory instead of ../ in #include.
...
Suggested by aKor.
llvm-svn: 55282
2008-08-24 12:30:46 +00:00
0c19df4871
Switch the asmprinter (.ll) and all the stuff it requires over to
...
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
llvm-svn: 55263
2008-08-23 22:23:09 +00:00
31099519d0
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
...
Is there way to avoid explicit target check?
llvm-svn: 55238
2008-08-23 15:53:19 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
9f0d0639ca
Make option variables static, so they won't cause nameclash
...
llvm-svn: 55203
2008-08-22 21:27:49 +00:00
fc4f64eed0
Reverting r55190, r55191, and r55192. They broke the build with this error message:
...
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1
llvm-svn: 55200
2008-08-22 20:51:05 +00:00
736779f088
Anyext tweaks for x86. When extloading a value to i32 or i64, choose
...
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.
llvm-svn: 55190
2008-08-22 19:19:31 +00:00
ed86f689cb
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
...
llvm-svn: 55186
2008-08-22 17:20:54 +00:00
dec51704ed
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
...
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
llvm-svn: 55163
2008-08-22 03:49:10 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
...
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
2fd7dbaf1d
If part of the mask is "undef", then ignore it as we don't care what goes into it.
...
llvm-svn: 55147
2008-08-21 22:36:36 +00:00
765d3e0013
Fix whitespace. No functionality change.
...
llvm-svn: 55146
2008-08-21 22:35:37 +00:00
9534ea03e8
Fix a number of byval / memcpy / memset related codegen issues.
...
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
llvm-svn: 55139
2008-08-21 21:00:15 +00:00
5c2ac4a5e0
Treat floating point ST1 the same as ST0 when lowering for a call result
...
llvm-svn: 55135
2008-08-21 19:54:16 +00:00
c6337ac069
Add libm-oriented ISD opcodes for rounding operations.
...
llvm-svn: 55130
2008-08-21 17:55:02 +00:00
f16134141d
Allow inline asm nodes with empty bodies inside JIT.
...
This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)
llvm-svn: 55128
2008-08-21 17:33:01 +00:00
d3582c9bda
Simplify SelectRoot's interface, and factor out some common code
...
from all targets.
llvm-svn: 55124
2008-08-21 16:36:34 +00:00
75eeeb399e
Clean up whitespace.
...
llvm-svn: 55117
2008-08-21 08:38:54 +00:00
c1270f8eac
unbreak the CBE on treeadd an many others.
...
llvm-svn: 55112
2008-08-21 05:51:43 +00:00
9371964f47
Use raw_ostream throughout the AsmPrinter.
...
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
814f291664
Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
...
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.
Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.
llvm-svn: 55078
2008-08-20 21:27:32 +00:00
02c84b8910
Simplify FastISel's constructor argument list, make the FastISel
...
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
llvm-svn: 55076
2008-08-20 21:05:57 +00:00
3ad7e96f8a
Clean up a dead return missed in r55055.
...
llvm-svn: 55057
2008-08-20 15:54:46 +00:00
8823b0d245
Tablegen generated code already tests the opcode value, so it's not
...
necessary to use dyn_cast in these predicates.
llvm-svn: 55055
2008-08-20 15:24:22 +00:00
c8f9da50ec
Use cast instead of dyn_cast.
...
llvm-svn: 55052
2008-08-20 14:50:24 +00:00
a21bdda961
Fix comment spacing.
...
llvm-svn: 55047
2008-08-20 13:46:21 +00:00
6f765f392c
Add remaining 64-bit atomic patterns for x86-64.
...
llvm-svn: 55029
2008-08-20 00:48:50 +00:00
f00f3055d8
Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.
...
Just expand it like the other X-bit sub_and_fetches.
llvm-svn: 55023
2008-08-20 00:28:16 +00:00
e79740851f
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
...
was already present, but not hooked up to anything.
llvm-svn: 55018
2008-08-19 23:09:18 +00:00
daef7f43af
Instantiate FastISel for X86.
...
llvm-svn: 55011
2008-08-19 21:45:35 +00:00
4619e93bd3
The X86 target will soon have an implementation of createFastISel.
...
llvm-svn: 55010
2008-08-19 21:32:53 +00:00
5afbf510aa
Add support for 8 and 16 bit forms of __sync
...
builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
llvm-svn: 54999
2008-08-19 18:47:28 +00:00
d7dd8b8aeb
add a note
...
llvm-svn: 54985
2008-08-19 06:22:16 +00:00
f076d5eea8
add a note
...
llvm-svn: 54964
2008-08-19 00:41:02 +00:00
927b5a5ac2
remove empty file
...
llvm-svn: 54950
2008-08-18 21:27:19 +00:00
4ebf3009ed
Unbreak cpp backend: upgrade output due to change in APInt API
...
llvm-svn: 54942
2008-08-18 20:03:45 +00:00
0d19699e52
ARM asm printer can't handle dwarf info yet.
...
llvm-svn: 54913
2008-08-18 08:52:48 +00:00
ab35bfdf18
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
...
llvm-svn: 54903
2008-08-17 19:22:34 +00:00
aa8ab4501a
Don't require Registry specializations to define random static variables.
...
llvm-svn: 54902
2008-08-17 19:08:34 +00:00
d930f913e6
Rename some GC classes so that their roll will hopefully be clearer.
...
In particular, Collector was confusing to implementors. Several
thought that this compile-time class was the place to implement
their runtime GC heap. Of course, it doesn't even exist at runtime.
Specifically, the renames are:
Collector -> GCStrategy
CollectorMetadata -> GCFunctionInfo
CollectorModuleMetadata -> GCModuleInfo
CollectorRegistry -> GCRegistry
Function::getCollector -> getGC (setGC, hasGC, clearGC)
Several accessors and nested types have also been renamed to be
consistent. These changes should be obvious.
llvm-svn: 54899
2008-08-17 18:44:35 +00:00
954553c4ce
Make it compile on VC2005:
...
- update VC projects.
- Add an overload to llvm::Stream for <<, since std::hex and std::dec have type std::ios_base& (*)(std::ios_base&) in VC++. (templating the function don't work, due to ambiguities)
- add ../ on several include in X86/AsmPrinter/
llvm-svn: 54898
2008-08-17 18:24:26 +00:00
17d28de8ac
Move ARM to pluggable asmprinter
...
llvm-svn: 54889
2008-08-17 13:55:10 +00:00
19fed1eb3d
Use correct name for PPC codegen library
...
llvm-svn: 54888
2008-08-17 13:54:44 +00:00
28dc9d0ad9
Factor out asmprinter out of ppc
...
llvm-svn: 54887
2008-08-17 13:54:28 +00:00
c5faeb82b5
Move X86 assembler printers into separate directory. This allows JIT-only users not to link it in (use 'x86codegen' llvm-config arg for this)
...
llvm-svn: 54886
2008-08-17 13:53:59 +00:00
17f7165f84
Rework the routines that convert AP[S]Int into a string. Now, instead of
...
returning an std::string by value, it fills in a SmallString/SmallVector
passed in. This significantly reduces string thrashing in some cases.
More specifically, this:
- Adds an operator<< and a print method for APInt that allows you to
directly send them to an ostream.
- Reimplements APInt::toString to be much simpler and more efficient
algorithmically in addition to not thrashing strings quite as much.
This speeds up llvm-dis on kc++ by 7%, and may also slightly speed up the
asmprinter. This also fixes a bug I introduced into the asmwriter in a
previous patch w.r.t. alias printing.
llvm-svn: 54873
2008-08-17 07:19:36 +00:00
16d5d3fba7
PPC/Linux normally uses named section for bss
...
llvm-svn: 54847
2008-08-16 12:59:02 +00:00
c3f3aea666
Use proper strings section name for PPC
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llvm-svn: 54846
2008-08-16 12:58:46 +00:00
93584cd5a0
Use correct name for TLS address resolution routine on x86-64
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llvm-svn: 54845
2008-08-16 12:58:29 +00:00
Mon P Wang