ef0b7cc2d5
On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
...
llvm-svn: 66776
2009-03-12 05:59:15 +00:00
8bb50e2344
Forgot to check-in this as part of 7761.
...
llvm-svn: 66763
2009-03-12 03:20:07 +00:00
f883419b2f
Banksel optimization is now based on the section names of symbols, since the symbols in one section will always be put into one bank.
...
llvm-svn: 66761
2009-03-12 02:10:45 +00:00
5637df37cd
Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the
...
assembly text output uses an indirect call ("call *") instead of a direct call.
llvm-svn: 66735
2009-03-11 23:01:47 +00:00
294943c99b
optimize i8 and i16 tls values.
...
llvm-svn: 66725
2009-03-11 22:40:04 +00:00
42adc73a2b
Add a -no-implicit-float flag. This acts like -soft-float, but may generate
...
floating point instructions that are explicitly specified by the user.
llvm-svn: 66719
2009-03-11 22:30:01 +00:00
4581bebf2a
It makes no sense to have a ODR version of common
...
linkage, so remove it.
llvm-svn: 66690
2009-03-11 20:14:15 +00:00
25c6a46a81
For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
...
llvm-svn: 66684
2009-03-11 18:47:57 +00:00
93e87652f2
fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll
...
llvm-svn: 66660
2009-03-11 16:14:25 +00:00
e2881053c9
Remove the one-definition-rule version of extern_weak
...
linkage: this linkage type only applies to declarations,
but ODR is only relevant to globals with definitions.
llvm-svn: 66650
2009-03-11 08:08:06 +00:00
ce6a26cb1a
Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
...
llvm-svn: 66645
2009-03-11 06:35:11 +00:00
248ad00afd
formatting change, reduce indentation. No functionality change.
...
llvm-svn: 66642
2009-03-11 05:48:52 +00:00
afb355f281
Mark the Defs and Uses of STATUS register correctly, plus some reformatting.
...
llvm-svn: 66540
2009-03-10 10:35:34 +00:00
b0d4009ec8
Add more information to the EFLAGS note.
...
llvm-svn: 66515
2009-03-10 00:26:23 +00:00
d5b35ee215
Add a note about EFLAGS optimization.
...
llvm-svn: 66508
2009-03-09 23:47:02 +00:00
0ee0da841d
ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.
...
llvm-svn: 66435
2009-03-09 20:25:39 +00:00
ce5dfb692a
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
...
llvm-svn: 66429
2009-03-09 19:15:00 +00:00
d5ac9d87b4
do not export all the X86FastISel symbols, ever.
...
llvm-svn: 66382
2009-03-08 18:44:31 +00:00
ec415efb44
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
...
llvm-svn: 66365
2009-03-08 04:02:49 +00:00
393ac62837
add a note.
...
llvm-svn: 66360
2009-03-08 03:04:26 +00:00
cfd1f7aa9f
add a note.
...
llvm-svn: 66359
2009-03-08 01:54:43 +00:00
12da8ce3d2
Introduce new linkage types linkonce_odr, weak_odr, common_odr
...
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
llvm-svn: 66339
2009-03-07 15:45:40 +00:00
ff659b5b86
Arithmetic instructions don't set EFLAGS bits OF and CF bits
...
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.
llvm-svn: 66318
2009-03-07 01:58:32 +00:00
c719d73eec
Don't use plain INC32 and DEC32 on x86-64; it needs
...
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.
llvm-svn: 66207
2009-03-05 21:32:23 +00:00
e014b193c9
When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
...
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.
llvm-svn: 66206
2009-03-05 21:29:28 +00:00
2c2f192c74
Fix the "test" optimization to recognize "dec" as an add of
...
negative one, as subtracts of immediates are canonicalized
to adds.
llvm-svn: 66180
2009-03-05 19:32:48 +00:00
55d7b2ac4f
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
...
llvm-svn: 66058
2009-03-04 19:44:21 +00:00
f8920d0c75
Correct this comment.
...
llvm-svn: 66057
2009-03-04 19:24:25 +00:00
cc329b567d
When using MachineInstr operand indices on SDNodes, the number
...
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.
llvm-svn: 66056
2009-03-04 19:23:38 +00:00
9edd616b59
Fix PR3666: isel calls to constant addresses.
...
llvm-svn: 66024
2009-03-04 06:48:53 +00:00
6728f892be
Revert r66004 for now; it's causing a variety of test failures.
...
llvm-svn: 66008
2009-03-04 03:54:19 +00:00
fe8d71f42a
Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
...
result from add, sub, inc, and dec instructions in simple cases.
llvm-svn: 66004
2009-03-04 02:33:24 +00:00
b8905c4e2c
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
...
llvm-svn: 65996
2009-03-04 01:41:49 +00:00
3a72265d41
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC
...
instructions. These aren't used yet.
llvm-svn: 65965
2009-03-03 19:53:46 +00:00
530e038940
Use early exit to reduce indentation. No functional change.
...
llvm-svn: 65962
2009-03-03 19:26:27 +00:00
92b551bc2b
Fix a bunch of Doxygen syntax issues. Escape special characters,
...
and put @file directives on their own comment line.
llvm-svn: 65920
2009-03-03 02:55:14 +00:00
85cefe8567
Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
...
arbitrary vector sizes. Add an optional MinSplatBits parameter to specify
a minimum for the splat element size. Update the PPC target to use the
revised interface.
llvm-svn: 65899
2009-03-02 23:24:16 +00:00
d8ea0e144e
Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
...
method in a BuildVectorSDNode "pseudo-class".
llvm-svn: 65747
2009-03-01 01:13:55 +00:00
d844dc305e
Added another darwin subtarget
...
llvm-svn: 65662
2009-02-28 00:25:30 +00:00
000421eade
Refactor TLS code and add some tests. The tests and expected results are:
...
pic | declaration | linkage | visibility |
!pic | declaration | external | default | tls1.ll tls2.ll | local exec
pic | declaration | external | default | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default | tls3.ll tls4.ll | initial exec
pic | !declaration | external | default | tls3-pic.ll tls4-pic.ll | general dynamic
!pic | declaration | external | hidden | tls7.ll tls8.ll | local exec
pic | declaration | external | hidden | X | local dynamic
!pic | !declaration | external | hidden | tls9.ll tls10.ll | local exec
pic | !declaration | external | hidden | X | local dynamic
!pic | declaration | internal | default | tls5.ll tls6.ll | local exec
pic | declaration | internal | default | X | local dynamic
The ones marked with an X have not been implemented since local dynamic is not implemented.
llvm-svn: 65632
2009-02-27 13:37:18 +00:00
4609dbe222
Alignment values for i64 and f64 on ppc64 were wrong,
...
possibly for the reason suggested by the comment.
No wonder it didn't work very well. This unblocks
bootstrap with assertions on ppc.
llvm-svn: 65601
2009-02-27 00:56:35 +00:00
40abb7b5d0
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.
...
llvm-svn: 65499
2009-02-26 03:12:02 +00:00
a49de9de2e
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
...
llvm-svn: 65482
2009-02-25 22:49:59 +00:00
5c10a3aa7f
Add a totally synthetic situation I came up with while looking at a bug in
...
related code.
llvm-svn: 65437
2009-02-25 06:52:48 +00:00
bb878288cb
Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
...
results via reference parameters.
This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.
llvm-svn: 65426
2009-02-25 03:12:50 +00:00
c5437ea429
Overhaul my earlier submission due to feedback. It's a large patch, but most of
...
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
llvm-svn: 65379
2009-02-24 08:30:20 +00:00
318d7376ba
Fast-isel can't do TLS yet, so it should fall back to SDISel
...
if it sees TLS addresses.
llvm-svn: 65341
2009-02-23 22:03:08 +00:00
9f8fddeed8
Only v1i16 (i.e. _m64) is returned via RAX / RDX.
...
llvm-svn: 65313
2009-02-23 09:03:22 +00:00
e684da3e5d
Generate better code for v8i16 shuffles on SSE2
...
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
llvm-svn: 65311
2009-02-23 08:49:38 +00:00
9ee052bcdc
Propagate debug loc info through prologue/epilogue.
...
llvm-svn: 65298
2009-02-23 00:42:30 +00:00
9d31aca679
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
...
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
llvm-svn: 65296
2009-02-22 23:36:09 +00:00
2448aa1d8d
Add a note.
...
llvm-svn: 65275
2009-02-22 08:13:45 +00:00
e4ffc030e2
Be bug compatible with gcc by returning MMX values in RAX.
...
llvm-svn: 65274
2009-02-22 08:05:12 +00:00
91193c0094
Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.
...
llvm-svn: 65273
2009-02-22 08:04:23 +00:00
42aae86590
Drop bunch of half-working stuff in the ext_weak linkage support.
...
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).
The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)
llvm-svn: 65230
2009-02-21 11:53:32 +00:00
82aa14fae8
Make sure this doesn't access .end() too.
...
llvm-svn: 65213
2009-02-21 01:11:36 +00:00
81ebf9a578
Make sure we don't dereference the .end() of the container.
...
llvm-svn: 65211
2009-02-21 01:07:26 +00:00
56759ee658
Propagate more debug loc infos. This also includes some code cleaning.
...
llvm-svn: 65207
2009-02-21 00:43:56 +00:00
5191934371
We need to propagate the debug location information even when dealing with the
...
prologue/epilogue.
llvm-svn: 65206
2009-02-21 00:32:08 +00:00
2a9bad5ac1
Support return of MMX values in 64-bit mode.
...
llvm-svn: 65152
2009-02-20 20:43:02 +00:00
87d5ca083b
add note about sin
...
llvm-svn: 65137
2009-02-20 18:42:06 +00:00
0f4c581c4a
Put code that generates debug labels into TableGen so that it can be used by
...
everyone.
llvm-svn: 64978
2009-02-18 23:12:06 +00:00
8cab4c44bb
Add explicit keywords.
...
llvm-svn: 64915
2009-02-18 16:37:45 +00:00
18d85e7403
Add support to the JIT for true non-lazy operation. When a call to a function
...
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT. The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd. A new interface for allocating and
updating empty stubs is provided.
Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.
Add support under a new ExecutionEngine flag for emitting the infomration
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue. This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.
llvm-svn: 64906
2009-02-18 08:31:02 +00:00
2af1f85f1f
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
...
llvm-svn: 64891
2009-02-18 05:45:50 +00:00
a40d5e14ab
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
...
llvm-svn: 64877
2009-02-18 02:19:52 +00:00
cf0da6c597
Remove trailing whitespace to reduce later commit patch noise.
...
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
llvm-svn: 64827
2009-02-17 22:15:04 +00:00
cba4b6f83d
add a horrible note
...
llvm-svn: 64719
2009-02-17 01:16:14 +00:00
3c50922ea0
--- Merging (from foreign repository) r64714 into '.':
...
U include/llvm/CodeGen/DebugLoc.h
U lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.
llvm-svn: 64715
2009-02-17 01:04:54 +00:00
2a4553ba5f
Delete trailing whitespace.
...
llvm-svn: 64694
2009-02-16 23:14:14 +00:00
f6ccacba36
MachineLICM now handles these cases.
...
llvm-svn: 64620
2009-02-15 23:24:52 +00:00
29705333e5
The x86-64 red zone is now being used.
...
llvm-svn: 64535
2009-02-14 03:30:05 +00:00
c2fde91703
Teach x86 target -soft-float.
...
llvm-svn: 64496
2009-02-13 22:36:38 +00:00
3a8bd17fdb
Remove non-DebugLoc versions of BuildMI from IA64, Mips.
...
llvm-svn: 64438
2009-02-13 02:34:39 +00:00
9bba902c83
Remove non-DebugLoc versions of BuildMI from X86.
...
There were some that might even matter in X86FastISel.
llvm-svn: 64437
2009-02-13 02:33:27 +00:00
57097d2a26
missed file
...
llvm-svn: 64436
2009-02-13 02:32:04 +00:00
215a925766
Remove non-DebugLoc versions of buildMI from Sparc.
...
llvm-svn: 64435
2009-02-13 02:31:35 +00:00
635f2a69d9
Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
...
llvm-svn: 64433
2009-02-13 02:30:42 +00:00
460bfeba8c
Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16.
...
llvm-svn: 64432
2009-02-13 02:29:03 +00:00
e9f623e27c
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
...
llvm-svn: 64431
2009-02-13 02:27:39 +00:00
b851a7853a
and one more file
...
llvm-svn: 64430
2009-02-13 02:26:21 +00:00
7647da67ea
Remove refs to non-DebugLoc versions of BuildMI from ARM.
...
llvm-svn: 64429
2009-02-13 02:25:56 +00:00
65c0fd4c44
Revert this. It was breaking stuff.
...
llvm-svn: 64428
2009-02-13 02:16:35 +00:00
1c21ac3066
Turn off the old way of handling debug information in the code generator. Use
...
the new way, where all of the information is passed on SDNodes and machine
instructions.
llvm-svn: 64427
2009-02-13 02:01:04 +00:00
baca6ed65e
Check in missing file.
...
llvm-svn: 64410
2009-02-12 23:24:44 +00:00
6b8c76a910
Eliminate a couple of non-DebugLoc BuildMI variants.
...
Modify callers.
llvm-svn: 64409
2009-02-12 23:08:38 +00:00
655775293f
Arrange to print constants that match "n" and "i" constraints
...
in inline asm as signed (what gcc does). Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.
llvm-svn: 64400
2009-02-12 20:58:09 +00:00
844deb73f4
fix PR3538 for ARM.
...
llvm-svn: 64384
2009-02-12 17:38:23 +00:00
4d4c702d5f
fix PR3538 for PPC
...
llvm-svn: 64383
2009-02-12 17:37:15 +00:00
aed3a4215b
fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
...
leaving them in the DAG and then getting selection errors. This is a
fix for PR3538.
llvm-svn: 64382
2009-02-12 17:33:11 +00:00
f6d609a227
Move debug loc info along when the spiller creates new instructions.
...
llvm-svn: 64342
2009-02-12 00:02:55 +00:00
27b508db9b
Propagate DebugLoc info for spiller call-backs.
...
llvm-svn: 64329
2009-02-11 21:51:19 +00:00
27f85854f9
Don't try to set an EFLAGS operand to dead if no instruction was created.
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This fixes a bug introduced by r61215.
llvm-svn: 64316
2009-02-11 19:50:24 +00:00
589a539423
Handle llvm.x86.sse2.maskmov.dqu in 64-bit.
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llvm-svn: 64240
2009-02-10 22:06:28 +00:00
df15f13c34
80 col violations.
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llvm-svn: 64237
2009-02-10 21:39:44 +00:00
c3f7b82628
Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section.
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llvm-svn: 64199
2009-02-10 04:20:26 +00:00
e5ade4a9a1
Implement FpSET_ST1_*.
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llvm-svn: 64186
2009-02-09 23:32:07 +00:00
a950e99dee
Use doxygen comment syntax.
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llvm-svn: 64150
2009-02-09 18:12:09 +00:00
64dfcacd5f
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
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suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
llvm-svn: 64124
2009-02-09 07:14:22 +00:00
1aca40e349
add a note.
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llvm-svn: 64093
2009-02-08 20:44:19 +00:00
9c310711bb
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
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No functional change.
llvm-svn: 64026
2009-02-07 19:59:05 +00:00
747e55bc9a
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
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ScheduleDAG's TLI member to use const.
llvm-svn: 64018
2009-02-07 16:15:20 +00:00
4ea526268c
Needs this file too.
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llvm-svn: 63993
2009-02-07 00:56:46 +00:00
62fd95d6ec
Get rid of the last non-DebugLoc versions of getNode!
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Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
llvm-svn: 63992
2009-02-07 00:55:49 +00:00
4e3e3deed3
Refactor some repeated logic into a separate function.
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llvm-svn: 63989
2009-02-07 00:43:41 +00:00
78fe44ed52
Make a comment a doxygen comment.
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llvm-svn: 63988
2009-02-07 00:42:54 +00:00
84935759d5
Remove more non-DebugLoc getNode variants. Use
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getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
llvm-svn: 63978
2009-02-06 23:05:02 +00:00
400dc2e2e4
Remove more non-DebugLoc versions of getNode.
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llvm-svn: 63969
2009-02-06 21:50:26 +00:00
b6b0aa2449
Record debug location information in the Dwarf writer.
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A simple test program shows that debugging works. :-)
llvm-svn: 63968
2009-02-06 21:45:08 +00:00
af8f994681
Use .size and .type on ELF systems; this helps tools that map
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addresses to symbols.
llvm-svn: 63962
2009-02-06 21:15:52 +00:00
ab8e4425a3
Eliminate remaining non-DebugLoc version of getTargetNode.
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llvm-svn: 63951
2009-02-06 19:16:40 +00:00
48d6bb9924
Print globl directive for variables with external linkage (global variables).
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llvm-svn: 63943
2009-02-06 18:24:59 +00:00
066757eea1
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
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llvm-svn: 63938
2009-02-06 17:43:24 +00:00
b5f0ec3eb7
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
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llvm-svn: 63936
2009-02-06 17:17:30 +00:00
2c4cf2752d
get rid of some non-DebugLoc getTargetNode variants.
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llvm-svn: 63909
2009-02-06 02:08:06 +00:00
9f3f72f144
Get rid of one more non-DebugLoc getNode and
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its corresponding getTargetNode. Lots of
caller changes.
llvm-svn: 63904
2009-02-06 01:31:28 +00:00
f80493bbfd
Remove a non-DebugLoc version of getNode.
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llvm-svn: 63889
2009-02-05 22:07:54 +00:00
64fdacc27f
A few more isAsCheapAsAMove.
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llvm-svn: 63852
2009-02-05 08:42:55 +00:00
b842d529a3
Reapply 63765. Patches for clang and llvm-gcc to follow.
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llvm-svn: 63812
2009-02-05 01:49:45 +00:00
12c572b6fa
Get rid of 3 non-DebugLoc getNode variants.
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llvm-svn: 63808
2009-02-05 01:01:16 +00:00
7ae8c8b108
Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg.
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llvm-svn: 63800
2009-02-05 00:20:09 +00:00
f08a47bb70
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
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Adjust callers.
llvm-svn: 63789
2009-02-04 23:02:30 +00:00
ae616c2c61
Reverting 63765. This broke the build of both clang
...
and llvm-gcc.
llvm-svn: 63786
2009-02-04 22:47:25 +00:00
021052a705
Remove non-DebugLoc versions of getLoad and getStore.
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Adjust the many callers of those versions.
llvm-svn: 63767
2009-02-04 20:06:27 +00:00
6ae3aa83d0
New feature: add support for target intrinsics being defined in the
...
target directories themselves. This also means that VMCore no longer
needs to know about every target's list of intrinsics. Future work
will include converting the PowerPC target to this interface as an
example implementation.
llvm-svn: 63765
2009-02-04 19:47:21 +00:00
e84a7911c4
Bill implemented this.
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llvm-svn: 63752
2009-02-04 19:09:07 +00:00
553fd7e1eb
add a note, this is why we're faster at SciMark-MonteCarlo with
...
SSE disabled.
llvm-svn: 63751
2009-02-04 19:08:01 +00:00
556d14d483
Minor code cleanups; no functionality change.
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llvm-svn: 63740
2009-02-04 17:28:58 +00:00
679073b420
Remove non-DebugLoc forms of the exotic forms
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of Lod and Sto; patch uses.
llvm-svn: 63716
2009-02-04 02:34:38 +00:00
f2bb6f09a3
Remove some more non-DebugLoc versions of construction
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functions, with callers adjusted to fit.
llvm-svn: 63705
2009-02-04 01:48:28 +00:00
85263882aa
Remove a few non-DebugLoc versions of node creation
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functions.
llvm-svn: 63703
2009-02-04 01:17:06 +00:00
4379a795fe
Fixes a case where we generate an incorrect mask for pshfhw in the presence
...
of undefs and incorrectly determining if we have punpckldq.
llvm-svn: 63702
2009-02-04 01:16:59 +00:00
bbf13f54e0
Patch up omissions in DebugLoc propagation.
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llvm-svn: 63693
2009-02-04 00:33:20 +00:00
0404dc11af
Need this file too.
...
llvm-svn: 63674
2009-02-03 22:26:34 +00:00
abf66b8343
Add some DL propagation to places that didn't
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have it yet. More coming.
llvm-svn: 63673
2009-02-03 22:26:09 +00:00
14f2d9dcbd
DebugLoc propgation
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llvm-svn: 63664
2009-02-03 21:48:12 +00:00
1eb1ef2cfd
DebugLoc propagation. done with file.
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llvm-svn: 63656
2009-02-03 20:21:25 +00:00
66e03e6f7b
DebugLoc propagation. 2/3 through file.
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llvm-svn: 63650
2009-02-03 19:33:06 +00:00
561d1226b6
Tevert part of the x86 subtarget logic changes: when -march=x86-64
...
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.
This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.
llvm-svn: 63642
2009-02-03 18:53:21 +00:00
e3c78361d3
Create DebugLoc information in FastISel. Several temporary methods were
...
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.
llvm-svn: 63584
2009-02-03 00:55:04 +00:00
7403751e16
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
...
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.
Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.
llvm-svn: 63575
2009-02-03 00:04:43 +00:00
e83866065b
Only force SSE level if it is not correct.
...
Add an assert to check HasX86_64 status.
llvm-svn: 63552
2009-02-02 21:57:34 +00:00
5dbd26ae0f
remove #if 0 code on Bill's request.
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llvm-svn: 63542
2009-02-02 20:23:02 +00:00
50aeb12d80
Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
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llvm-svn: 63521
2009-02-02 16:53:06 +00:00
dc636c4080
ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero.
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llvm-svn: 63509
2009-02-02 09:15:04 +00:00
4988c597b3
Add comment.
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llvm-svn: 63506
2009-02-02 08:19:07 +00:00
50e15bdf81
Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.
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llvm-svn: 63505
2009-02-02 08:07:36 +00:00
a2d1f35e9a
Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for
...
var-args, and don't allow FP return values
llvm-svn: 63495
2009-02-01 18:15:56 +00:00
3ed768868d
Fix PR3453 and probably a bunch of other potential
...
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.
llvm-svn: 63494
2009-02-01 18:06:53 +00:00
555a375bb6
Make LowerCallTo and LowerArguments take a DebugLoc
...
argument. Adjust all callers and overloaded versions.
llvm-svn: 63444
2009-01-30 23:10:59 +00:00
Evan Cheng