OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
404,540 Commits 31 Branches 0 Tags 2.2 GiB
Commit Graph

6 Commits

Author SHA1 Message Date
Sam Elliott 5f9ecc5d85 [RISCV] Indirect branch generation in position independent code 
This fixes the "Unable to insert indirect branch" fatal error sometimes
seen when generating position-independent code.

Patch by msizanoen1

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D84833
 2020-08-17 13:09:26 +01:00
Fangrui Song 4d5fd0ee5e [MC][RISCV] Set UseIntegratedAssembler to true 
to align with most other targets. Also, -fintegrated-as is the default
for clang -target riscv*.
 2020-07-12 21:04:48 -07:00
Alex Bradbury 1ffceaa543 [RISCV] Match GNU tools canonical JALR and add aliases 
The canonical GNU form of JALR resembles a load/store instruction rather
than placing the immediate offset as a separate argument, so match this
behaviour. Also add parser-only aliases for the three-operand form, and
add other shorter aliases also emitted by GNU tools.

Differential Revision: https://reviews.llvm.org/D55277
Patch by James Clarke.

llvm-svn: 366179
 2019-07-16 04:56:43 +00:00
Alex Bradbury 5dabe03b41 [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llvm-svn: 361493
 2019-05-23 12:43:13 +00:00
Alex Bradbury 7d6aa1f7ae [RISCV] Implement frame pointer elimination 
llvm-svn: 322839
 2018-01-18 11:34:02 +00:00
Alex Bradbury 315cd3ace4 [RISCV] Implement support for the BranchRelaxation pass 
Branch relaxation is needed to support branch displacements that overflow the
instruction's immediate field.

Differential Revision: https://reviews.llvm.org/D40830

llvm-svn: 322224
 2018-01-10 21:05:07 +00:00