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Author SHA1 Message Date
Carl Ritson 98f48723f2 [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 
Add SReg_224, VReg_224, AReg_224, etc.
Link 224-bit types with v7i32/v7f32.
Link existing 192-bit types to newly added v3i64/v3f64/v6i32/v6f32.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D104622
 2021-06-24 12:41:22 +09:00
Mirko Brkusanin 7c88d13fd1 [AMDGPU] Prefer SplitVectorLoad/Store over expandUnalignedLoad/Store 
ExpandUnalignedLoad/Store can sometimes produce unnecessary copies to
temporary stack slot. We should prefer splitting vectors if possible.

Differential Revision: https://reviews.llvm.org/D88882
 2020-10-08 10:17:15 +02:00
Mirko Brkusanin 380087e6c9 [AMDGPU] Add test with redundant copies to temporary stack slot produced by expandUnalignedLoad 
Differential Revision: https://reviews.llvm.org/D88895
 2020-10-08 10:17:15 +02:00