4 Commits

Author	SHA1	Message	Date
Misha Brukman	b440243e94	Remove trailing whitespace ... llvm-svn: 21425	2005-04-21 23:30:14 +00:00
Nate Begeman	f67f3bf627	Initial support for allocation condition registers ... llvm-svn: 21246	2005-04-12 07:04:16 +00:00
Nate Begeman	c6b63cd2ed	Add ori reg, reg, 0 as a move instruction. This can be generated from ... loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr llvm-svn: 16825	2004-10-07 22:26:12 +00:00
Misha Brukman	116f9277f6	PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* ... llvm-svn: 15850	2004-08-17 04:55:41 +00:00