Commit Graph

43511 Commits

Author SHA1 Message Date
Andrew Litteken e6ae623314 [IROutliner] Adding support for consolidating functions with different output arguments.
Certain regions can have values introduced inside the region that are
used outside of the region. These may not be the same for each similar
region, so we must create one over arching set of arguments for the
consolidated function.

We do this by iterating over the outputs for each extracted function,
and creating as many different arguments to encapsulate the different
outputs sets. For each output set, we create a different block with the
necessary stores from the value to the output register. There is then
one switch statement, controlled by an argument to the function, to
differentiate which block to use.

Changed Tests for consistency:
llvm/test/Transforms/IROutliner/extraction.ll
llvm/test/Transforms/IROutliner/illegal-assumes.ll
llvm/test/Transforms/IROutliner/illegal-memcpy.ll
llvm/test/Transforms/IROutliner/illegal-memmove.ll
llvm/test/Transforms/IROutliner/illegal-vaarg.ll

Tests to test new functionality:
llvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll
llvm/test/Transforms/IROutliner/outlining-remapped-outputs.ll
llvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87296
2020-12-28 16:17:07 -06:00
Thomas Lively 5e09e9979b [WebAssembly] Prototype extending pairwise add instructions
As proposed in https://github.com/WebAssembly/simd/pull/380. This commit makes
the new instructions available only via clang builtins and LLVM intrinsics to
make their use opt-in while they are still being evaluated for inclusion in the
SIMD proposal.

Depends on D93771.

Differential Revision: https://reviews.llvm.org/D93775
2020-12-28 14:11:14 -08:00
Juneyoung Lee 0f2c180163 [ValueTracking] Implement impliesPoison
This PR adds impliesPoison(ValAssumedPoison, V) that returns true if V is
poison under the assumption that ValAssumedPoison is poison.

For example, impliesPoison('icmp X, 10', 'icmp X, Y') return true because
'icmp X, Y' is poison if 'icmp X, 10' is poison.

impliesPoison can be used for sound optimization of select, as discussed in
D77868.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D78152
2020-12-29 06:50:38 +09:00
Nikita Popov 4a16c507cb [InstCombine] Disable unsafe select transform behind a flag
This disables the poison-unsafe select -> and/or transform behind
a flag (we continue to perform the fold by default). This is intended
to simplify evaluation and testing while we teach various passes
to directly recognize the select pattern.

This only disables the main select -> and/or transform. A number of
related ones are instead changed to canonicalize to the a ? b : false
and a ? true : b forms which represent and/or respectively. This
requires a bit of care to avoid infinite loops, as we do not want
!a ? b : false to be converted into a ? false : b.

The basic idea here is the same as D93065, but keeps the change
behind a flag for now.

Differential Revision: https://reviews.llvm.org/D93840
2020-12-28 22:43:52 +01:00
Zakk Chen e673d40199 [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics.
Define those intrinsics and lower to V instructions.

Use update_llc_test_checks.py for viota.m tests to check
earlyclobber is applied correctly.
mask viota.m tests uses the same argument as input and mask for
avoid dependency of D93364.

We work with @rogfer01 from BSC to come out this patch.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D93823
2020-12-28 05:54:18 -08:00
Yevgeny Rouban d76c1d2247 [RS4GC] Lazily set changed flag when folding single entry phis
The function FoldSingleEntryPHINodes() is changed to return if
it has changed IR or not. This return value is used by RS4GC to
set the MadeChange flag respectively.

Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D93810
2020-12-28 10:54:21 +07:00
Kazu Hirata 789d250613 [CodeGen, Transforms] Use *Map::lookup (NFC) 2020-12-27 09:57:27 -08:00
Nikita Popov 0af42d3dc7 [PatternMatch][LVI] Handle select-form and/or in LVI
Following the discussion in D93065, this adds m_LogicalAnd() and
m_LogicalOr() matchers, that match A && B and A || B logical
operations, either as bitwise operations or select expressions.
As an example usage, LVI is adapted to use these matchers for its
condition reasoning.

The plan here is to switch other parts of LLVM that reason about
and/or of conditions to also support the select forms, and then
merge D93065 (or a variant thereof) to disable the poison-unsafe
select to and/or transform.

Differential Revision: https://reviews.llvm.org/D93827
2020-12-27 17:39:02 +01:00
Monk Chiang 622ea9cf74 [RISCV] Define vector widening reduction intrinsic.
Define vwredsumu/vwredsum/vfwredosum/vfwredsum

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D93807
2020-12-26 21:42:30 +08:00
Kazu Hirata 46bea9b297 [Local] Remove unused function RemovePredecessorAndSimplify (NFC)
The last use of the function was removed on Sep 29, 2010 in commit
99c985c37d.
2020-12-25 09:35:20 -08:00
Nikita Popov b96a6ea0a9 [BasicAA] Make sure context instruction is symmetric
D71264 started using a context instruction in a computeKnownBits()
call. However, if aliasing between two GEPs is checked, then the
choice of context instruction will be different for alias(GEP1, GEP2)
and alias(GEP2, GEP1), which is not supposed to happen.

Resolve this by remembering which GEP a certain VarIndex belongs to,
and use that as the context instruction. This makes the choice of
context instruction predictable and symmetric.

It should be noted that this choice of context instruction is
non-optimal (just like the previous choice): The AA query result is
only valid at points that are reachable from *both* instructions.
Using either one of them is conservatively correct, but a larger
context may also be valid to use.

Differential Revision: https://reviews.llvm.org/D93183
2020-12-25 11:35:46 +01:00
Georgii Rymar 438bc157a4 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_ELFT define (ELFTypes.h).
This allows to get rid of lots for typedefs/usings from many places.

Differential revision: https://reviews.llvm.org/D93801
2020-12-25 11:39:05 +03:00
Zakk Chen da4a637e99 [RISCV] Define vpopc/vfirst intrinsics.
Define vpopc/vfirst intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93795
2020-12-24 19:44:34 -08:00
Zakk Chen 351c216f36 [RISCV] Define vector mask-register logical intrinsics.
Define vector mask-register logical intrinsics and lower them
to V instructions. Also define pseudo instructions vmmv.m
and vmnot.m.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D93705
2020-12-24 18:59:05 -08:00
ShihPo Hung 912740a864 [RISCV] Add intrinsics for vrgather instruction
This patch defines vrgather intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential revision: https://reviews.llvm.org/D93797
2020-12-24 18:16:02 -08:00
Monk Chiang afd03cd335 [RISCV] Define vector single-width reduction intrinsic.
integer group:
vredsum/vredmaxu/vredmax/vredminu/vredmin/vredand/vredor/vredxor
float group:
vfredosum/vfredsum/vfredmax/vfredmin

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D93746
2020-12-25 09:56:01 +08:00
Roman Lebedev b3021a72a6
[IR][InstCombine] Add m_ImmConstant(), that matches on non-ConstantExpr constants, and use it
A pattern to ignore ConstantExpr's is quite common, since they frequently
lead into infinite combine loops, so let's make writing it easier.
2020-12-24 21:20:47 +03:00
Kazu Hirata e457896a6e [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC)
The last use of the function was removed on Sep 13, 2010 in commit
1094c80281.
2020-12-24 09:17:58 -08:00
Simon Pilgrim 6895581fd2 [Support] Add KnownBits::getSignedMinValue/getSignedMaxValue helpers.
Add unit test coverage - a followup will update InstCombineCompares.cpp to use this and could be used by D86578 as well.
2020-12-24 14:10:12 +00:00
Simon Pilgrim fb46895308 [Support] Explicitly state that KnownBits::getMinValue/getMaxValue are UNSIGNED values. NFCI.
Update the comment to make this clear, following the same approach as APInt.
2020-12-24 14:10:11 +00:00
Kazu Hirata 200b15af45 [Analysis] Remove spliceFunction (NFC)
The function was introduced without a user on Jan 3, 2011 in commit
0f87ca7733.  We still don't have a user
yet.
2020-12-23 21:57:25 -08:00
Andrew Litteken 48ad8194a5 [IRSim] Adding support for isomorphic predicates
Some predicates, can be considered the same as long as the operands are
flipped. For example, a > b gives the same result as b > a. This maps
instructions in a greater than form, to their appropriate less than
form, swapping the operands in the IRInstructionData only, allowing for
more flexible matching.

Tests:

llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll
llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp

Reviewers: jroelofs, paquette

Recommit of commit 0503926602

Differential Revision: https://reviews.llvm.org/D87310
2020-12-23 19:42:35 -06:00
Andrew Litteken 45a4f34bd1 Revert "[IRSim] Adding support for isomorphic predicates"
Reverting due to unit test errors between commits.

This reverts commit 0503926602.
2020-12-23 15:14:19 -06:00
Andrew Litteken 0503926602 [IRSim] Adding support for isomorphic predicates
Some predicates, can be considered the same as long as the operands are
flipped. For example, a > b gives the same result as b > a. This maps
instructions in a greater than form, to their appropriate less than
form, swapping the operands in the IRInstructionData only, allowing for
more flexible matching.

Tests:

llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll
llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87310
2020-12-23 15:02:00 -06:00
Andrew Litteken cce473e0c5 [IRSim] Adding commutativity matching to structure checking
Certain instructions, such as adds and multiplies can have the operands
flipped and still be considered the same. When we are analyzing
structure, this gives slightly more flexibility to create a mapping from
one region to another. We can add both operands in a corresponding
instruction to an operand rather than just the exact match. We then try
to eliminate items from the set, until there is only one valid mapping
between the regions of code.

We do this for adds, multiplies, and equality checking. However, this is
not done for floating point instructions, since the order can still
matter in some cases.

Tests:

llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
llvm/test/Transforms/IROutliner/outlining-commutative.ll
llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87311
2020-12-23 15:02:00 -06:00
Nico Weber 1876a2914f Revert more changes that landed on top of 741978d727
This should've been in 7ad666798f but wasn't.

Squashes these twoc commits:
Revert "[clang][cli] Let denormalizer decide how to render the option based on the option class"
This reverts commit 70410a2649.

Revert "[clang][cli] Implement `getAllArgValues` marshalling"
This reverts commit 63a24816f5.
2020-12-23 14:20:21 -05:00
Andrew Litteken b1191c8438 [IROutliner] Adding support for elevating constants that are not the same in each region to arguments
When there are constants that have the same structural location, but not
the same value, between different regions, we cannot simply outline the
region. Instead, we find the constants that are not the same in each
location, and promote them to arguments to be passed into the respective
functions. At each call site, we pass the constant in as an argument
regardless of type.

Added/Edited Tests:

llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll
llvm/test/Transforms/IROutliner/outlining-different-constants.ll
llvm/test/Transforms/IROutliner/outlining-different-globals.ll

Reviewers: paquette, jroelofs

Differential Revision: https://reviews.llvm.org/D87294
2020-12-23 13:03:05 -06:00
Craig Topper e0110a4740 [RISCV] Add intrinsics for vfmv.v.f
Also include a special case pattern to use vmv.v.x vd, zero when
the argument is 0.0.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D93672
2020-12-23 10:50:48 -08:00
Nico Weber 7ad666798f Revert 741978d727 and things that landed on top of it.
741978d727 made clang produce output that's 2x as large at least in
sanitizer builds. https://reviews.llvm.org/D83892#2470185 has a
standalone repro.

This reverts the following commits:

Revert "[clang][cli] Port CodeGenOpts simple string flags to new option parsing system"
This reverts commit 95d3cc67ca.

Revert "[clang][cli] Port LangOpts simple string based options to new option parsing system"
This reverts commit aec2991d08.

Revert "[clang][cli] Streamline MarshallingInfoFlag description"
This reverts commit 27b7d64688.

Revert "[clang][cli] Port LangOpts option flags to new option parsing system"
This reverts commit 383778e217.

Revert "[clang][cli] Port CodeGen option flags to new option parsing system"
This reverts commit 741978d727.
2020-12-23 12:52:11 -05:00
Paul C. Anagnostopoulos e122a71a0a [TableGen] Add the !substr() bang operator
Update the documentation and add a test.

Build failed: Change SIZE_MAX to std::numeric_limits<int64_t>::max().

Differential Revision: https://reviews.llvm.org/D93419
2020-12-23 10:59:33 -05:00
Evgeniy Brevnov 9fb074e7bb [BPI] Improve static heuristics for "cold" paths.
Current approach doesn't work well in cases when multiple paths are predicted to be "cold". By "cold" paths I mean those containing "unreachable" instruction, call marked with 'cold' attribute and 'unwind' handler of 'invoke' instruction. The issue is that heuristics are applied one by one until the first match and essentially ignores relative hotness/coldness
 of other paths.

New approach unifies processing of "cold" paths by assigning predefined absolute weight to each block estimated to be "cold". Then we propagate these weights up/down IR similarly to existing approach. And finally set up edge probabilities based on estimated block weights.

One important difference is how we propagate weight up. Existing approach propagates the same weight to all blocks that are post-dominated by a block with some "known" weight. This is useless at least because it always gives 50\50 distribution which is assumed by default anyway. Worse, it causes the algorithm to skip further heuristics and can miss setting more accurate probability. New algorithm propagates the weight up only to the blocks that dominates and post-dominated by a block with some "known" weight. In other words, those blocks that are either always executed or not executed together.

In addition new approach processes loops in an uniform way as well. Essentially loop exit edges are estimated as "cold" paths relative to back edges and should be considered uniformly with other coldness/hotness markers.

Reviewed By: yrouban

Differential Revision: https://reviews.llvm.org/D79485
2020-12-23 22:47:36 +07:00
Simon Moll acaa6e4260 [NFC] Uniquify 'const' in TargetTransformInfoImpl.h
Some member functions of class TargetTransformInfoImplBase in
TargetTransformInfoImpl.h are marked const while others are not. Yet all
of the should be marked const since they are just providing default TTI
values. This patch fixes the inconsistency.

Authored-by: Jinzheng Tu <b1f6c1c4@gmail.com>

Reviewed By: simoll

Differential revision: https://reviews.llvm.org/D93573
2020-12-23 14:21:41 +01:00
ShihPo Hung 6301871d06 [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac instructions
This patch defines vfwmacc, vfwnmacc, vfwmsc, vfwnmsac intrinsics
and lower to V instructions.
We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93693
2020-12-23 00:42:04 -08:00
Zakk Chen 032600b9ae [RISCV] Define vmerge/vfmerge intrinsics.
Define vmerge/vfmerge intrinsics and lower to V instructions.

Include support for vector-vector vfmerge by vmerge.vvm.

We work with @rogfer01 from BSC to come out this patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93674
2020-12-23 00:07:09 -08:00
Evandro Menezes 4d47944393 [RISCV] Define the vfmin, vfmax RVV intrinsics
Define the vfmin, vfmax IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com>

Differential Revision: https://reviews.llvm.org/D93673
2020-12-23 00:27:38 -06:00
Matt Arsenault 581d13f8ae GlobalISel: Return APInt from getConstantVRegVal
Returning int64_t was arbitrarily limiting for wide integer types, and
the functions should handle the full generality of the IR.

Also changes the full form which returns the originally defined
vreg. Add another wrapper for the common case of just immediately
converting to int64_t (arguably this would be useful for the full
return value case as well).

One possible issue with this change is some of the existing uses did
break without conversion to getConstantVRegSExtVal, and it's possible
some without adequate test coverage are now broken.
2020-12-22 22:23:58 -05:00
ShihPo Hung ad0a7ad950 [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf[n]msub instructions
This patch defines vfmadd/vfnmacc, vfmsac/vfnmsac, vfmadd/vfnmadd,
and vfmsub/vfnmsub lower to V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93691
2020-12-22 18:34:00 -08:00
ShihPo Hung 4268783998 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions
This patch defines vwmacc[u|su|us] intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93675
2020-12-22 18:17:39 -08:00
ShihPo Hung c8874464b5 [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction
This patch adds intrinsics for vslide1up, vslide1down, vfslide1up, vfslide1down.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93608
2020-12-22 18:14:22 -08:00
Matt Arsenault 5bec082834 VirtRegMap: Use Register 2020-12-22 20:56:14 -05:00
Arthur O'Dwyer 22cf54a7fb Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it means reinterpret_cast. NFC.
Differential Revision: https://reviews.llvm.org/D76572
2020-12-22 19:54:29 -05:00
Arnold Schwaighofer 333108e8be Add a llvm.coro.end.async intrinsic
The llvm.coro.end.async intrinsic allows to specify a function that is
to be called as the last action before returning. This function will be
inlined after coroutine splitting.

This function can contain a 'musttail' call to allow for guaranteed tail
calling as the last action.

Differential Revision: https://reviews.llvm.org/D93568
2020-12-22 10:52:28 -08:00
sameeran joshi 1aa10ab2e1 Revert "[Flang][openmp][5.0] Add task_reduction clause."
This reverts commit 9a7895dc20.
Reverting due to missing Co-author attribution.

https://reviews.llvm.org/D93105
2020-12-22 23:53:51 +05:30
Nathan James 5d10b8ad59
[ADT] Add resize_for_overwrite method to SmallVector.
Analagous to the std::make_(unqiue|shared)_for_overwrite added in c++20.
If T is POD, and the container gets larger, any new values added wont be initialized.
This is useful when using SmallVector as a buffer where its planned to overwrite any potential new values added.
If T is not POD, `new (Storage) T` functions identically to `new (Storage) T()` so this will function identically to `resize(size_type)`.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D93532
2020-12-22 17:18:59 +00:00
sameeran joshi 9a7895dc20 [Flang][openmp][5.0] Add task_reduction clause.
See OMP-5.0 2.19.5.5 task_reduction Clause.
To add a positive test case we need `taskgroup` directive which is not added hence skipping the test.
This is a dependency for `taskgroup` construct.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D93105
2020-12-22 22:34:38 +05:30
Nandor Licker 0586f048d7 [RISCV] Basic jump table lowering
This patch enables jump table lowering in the RISC-V backend.

In addition to the test case included, the new lowering was
tested by compiling the OCaml runtime and running it under qemu.

Differential Revision: https://reviews.llvm.org/D92097
2020-12-22 15:05:54 +00:00
Paul C. Anagnostopoulos 5b37f0d970 [MCInstrDesc] [TableGen] Reduce size of MCOperandInfo instances.
Differential Revision: https://reviews.llvm.org/D93326
2020-12-22 09:44:30 -05:00
Jan Svoboda 63a24816f5 [clang][cli] Implement `getAllArgValues` marshalling
This infrastructure can be used ~30 more command line options.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D93631
2020-12-22 14:11:16 +01:00
sameeran joshi 1a6f43991f [Flang][openmp][5/5] Make dist_schedule clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpDistScheduleClause` clause part of `OmpClause`.
The unparse function for `OmpDistScheduleClause` is adapted since the keyword
and parenthesis are issued by the corresponding unparse function for
`parser::OmpClause::DistSchedule`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93644
2020-12-22 14:32:33 +05:30
sameeran joshi e282ae57da [Flang][openmp][4/5] Make nowait clause part of OmpClause
After discussion in `D93482` we found that the some of the clauses were not
following the common OmpClause convention.

The benefits of using OmpClause:
- Functionalities from structure checker are mostly aligned to work with
  `llvm::omp::Clause`.
- The unparsing as well can take advantage.
- Homogeneity with OpenACC and rest of the clauses in OpenMP.
- Could even generate the parser with TableGen, when there is homogeneity.
- It becomes confusing when to use `flangClass` and `flangClassValue` inside
  TableGen, if incase we generate parser using TableGen we could have only a
  single `let expression`.

This patch makes `OmpNoWait` clause part of `OmpClause`.

Reviewed By: clementval, kiranktp

Differential Revision: https://reviews.llvm.org/D93643
2020-12-22 14:02:19 +05:30