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5 Commits

Author SHA1 Message Date
Mircea Trofin 55ea639d3c [NFC] Removed unused prefixes in llvm/test/CodeGen/AArch64 
Differential Revision: https://reviews.llvm.org/D92943
 2020-12-09 12:47:51 -08:00
Paul Walker 27f3d51b4e [SVE] Lower fixed length vector fneg and fsqrt operations. 
Also updates sve-fp.ll to use fneg directly.

Differential Revision: https://reviews.llvm.org/D88683
 2020-10-06 10:48:16 +01:00
Paul Walker ab6a517ea4 Fix "CHECK-LABEL: @" typos in llvm/test/CodeGen/AArch64/sve-fixed-length-*.ll 2020-08-10 20:07:45 +01:00
Paul Walker 6384ec4099 [SVE] Add lowering for fixed length vector fdiv, fma, fmul and fsub operations. 
Differential Revision: https://reviews.llvm.org/D84034
 2020-07-20 11:57:34 +00:00
Paul Walker 3a98d5d7e7 [SVE] Code generation for fixed length vector adds. 
Summary:
Teach LowerToPredicatedOp to lower fixed length vector operations.

Add AArch64ISD nodes and isel patterns for predicated integer
and floating point adds.

Together this enables SVE code generation for fixed length vector adds.

Reviewers: rengolin, efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82483
 2020-06-26 19:54:41 +00:00