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Author SHA1 Message Date
Cameron McInally 8372e47bb9 [NFCI][SVE] Move fixed length i32/i64 SDIV tests 
Move fixed length SDIV tests from sve-fixed-length-int-arith.ll to sve-fixed-length-int-div.ll. The former uses CHECK lines that verify legalization decisions. That's overkill for the i8/i16 SDIV tests, since they have a tricky legalization.
 2020-08-20 14:46:26 -05:00
Cameron McInally 92593f9e77 [SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors. 
Differential Revision: https://reviews.llvm.org/D85982
 2020-08-14 18:47:22 -05:00
Paul Walker d542feb8e4 [SVE] Lower fixed length vector integer subtract operations. 
Differential Revision: https://reviews.llvm.org/D85665
 2020-08-11 11:32:12 +01:00
Paul Walker ab6a517ea4 Fix "CHECK-LABEL: @" typos in llvm/test/CodeGen/AArch64/sve-fixed-length-*.ll 2020-08-10 20:07:45 +01:00
Paul Walker 3ed59b775d [SVE] Implement lowering for fixed length vector multiplication. 
NOTE: Also uses SVE code generation for NEON size vectors, instead
of expanding i64 based vector multiplications.

Differential Revision: https://reviews.llvm.org/D85327
 2020-08-06 11:01:39 +01:00
Paul Walker 3a98d5d7e7 [SVE] Code generation for fixed length vector adds. 
Summary:
Teach LowerToPredicatedOp to lower fixed length vector operations.

Add AArch64ISD nodes and isel patterns for predicated integer
and floating point adds.

Together this enables SVE code generation for fixed length vector adds.

Reviewers: rengolin, efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82483
 2020-06-26 19:54:41 +00:00