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7 Commits

Author SHA1 Message Date
Cameron McInally abe14485fe [SVE] Fix VBITS_GE_256 typo in fixed-width tests. 
This seems to be a typo that propagated to a number of tests. Replace VBITS_GE_256 with CHECK. There is no VBITS_GE_256.
 2020-10-12 14:31:34 -05:00
Amara Emerson 322d0afd87 [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 
This change renames the intrinsics to not have "experimental" in the name.

The autoupgrader will handle legacy intrinsics.

Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html

Differential Revision: https://reviews.llvm.org/D88787
 2020-10-07 10:36:44 -07:00
Cameron McInally 6bec45e255 [SVE] Add legalisation tests to sve-fixed-length-int-reduce.ll 2020-10-05 16:05:44 -05:00
Cameron McInally 01c95f7942 [SVE] Fix typo in CHECK lines for sve-fixed-length-int-reduce.ll 2020-09-29 10:12:58 -05:00
Cameron McInally 9b0b09671c [SVE] Lower fixed length VECREDUCE_[UMAX|UMIN] to Scalable 
Essentially the same as the signed variants from D88259. Also includes a clean up of the lowering function.

Differential Revision: https://reviews.llvm.org/D88317
 2020-09-28 09:29:00 -05:00
Cameron McInally e2ccf7f178 [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable 
This patch is pretty similar to the VECREDUCE_ADD patch, with some minor tweaks.

Results from the AArch64ISD::[SMAX|SMIN]V_PRED return element sized results. This requires an ANY_EXTEND for results < 32-bits, since Legalization promotes those results.

There is no NEON i64 vector support for SMAXV|SMINV, so use SVE for those.

Differential Revision: https://reviews.llvm.org/D88259
 2020-09-25 09:58:17 -05:00
Cameron McInally db40a74344 [SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable 
Differential Revision: https://reviews.llvm.org/D87796
 2020-09-23 09:08:07 -05:00