1c171b121a
Explicitly disallow predication in Thumb1 assembly.
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llvm-svn: 138562
2011-08-25 17:23:55 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
d80d169a04
Thumb parsing and encoding for STM.
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llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
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llvm-svn: 138344
2011-08-23 18:13:04 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
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llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
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llvm-svn: 138308
2011-08-22 23:47:13 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
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llvm-svn: 138295
2011-08-22 23:17:34 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
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llvm-svn: 138287
2011-08-22 23:01:07 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
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llvm-svn: 138258
2011-08-22 18:50:36 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
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llvm-svn: 138131
2011-08-19 22:51:03 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
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llvm-svn: 138124
2011-08-19 22:30:46 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
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llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
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llvm-svn: 138076
2011-08-19 20:46:54 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
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llvm-svn: 138063
2011-08-19 19:29:25 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
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llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
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llvm-svn: 138059
2011-08-19 18:49:59 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
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llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
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llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
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llvm-svn: 138047
2011-08-19 17:55:24 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
6ddb568ab8
Add missing 'break'.
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llvm-svn: 137941
2011-08-18 16:08:39 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
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llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
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llvm-svn: 137889
2011-08-17 22:49:09 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
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llvm-svn: 137788
2011-08-16 23:57:34 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
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llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
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llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
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llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
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llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
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Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
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llvm-svn: 137389
2011-08-11 23:51:13 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
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llvm-svn: 137367
2011-08-11 22:05:09 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
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llvm-svn: 137353
2011-08-11 21:17:22 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
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llvm-svn: 137342
2011-08-11 20:28:23 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
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llvm-svn: 137331
2011-08-11 19:22:40 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
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Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
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llvm-svn: 137260
2011-08-10 22:42:16 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
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Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
f7164b2cfd
Fix typo. Not quite sure how that slipped in there.
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llvm-svn: 137245
2011-08-10 20:49:18 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
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llvm-svn: 137244
2011-08-10 20:29:19 +00:00
95466ce63b
ARM load/store label parsing.
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Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
llvm-svn: 137064
2011-08-08 20:59:31 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
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Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach