Summary:
This patch replaces the CUDA specific action by a generic offload action. The offload action may have multiple dependences classier in “host” and “device”. The way this generic offloading action is used is very similar to what is done today by the CUDA implementation: it is used to set a specific toolchain and architecture to its dependences during the generation of jobs.
This patch also proposes propagating the offloading information through the action graph so that that information can be easily retrieved at any time during the generation of commands. This allows e.g. the "clang tool” to evaluate whether CUDA should be supported for the device or host and ptas to easily retrieve the target architecture.
This is an example of how the action graphs would look like (compilation of a single CUDA file with two GPU architectures)
```
0: input, "cudatests.cu", cuda, (host-cuda)
1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
2: compiler, {1}, ir, (host-cuda)
3: input, "cudatests.cu", cuda, (device-cuda, sm_35)
4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_35)
5: compiler, {4}, ir, (device-cuda, sm_35)
6: backend, {5}, assembler, (device-cuda, sm_35)
7: assembler, {6}, object, (device-cuda, sm_35)
8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {7}, object
9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {6}, assembler
10: input, "cudatests.cu", cuda, (device-cuda, sm_37)
11: preprocessor, {10}, cuda-cpp-output, (device-cuda, sm_37)
12: compiler, {11}, ir, (device-cuda, sm_37)
13: backend, {12}, assembler, (device-cuda, sm_37)
14: assembler, {13}, object, (device-cuda, sm_37)
15: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {14}, object
16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {13}, assembler
17: linker, {8, 9, 15, 16}, cuda-fatbin, (device-cuda)
18: offload, "host-cuda (powerpc64le-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {17}, ir
19: backend, {18}, assembler
20: assembler, {19}, object
21: input, "cuda", object
22: input, "cudart", object
23: linker, {20, 21, 22}, image
```
The changes in this patch pass the existent regression tests (keeps the existent functionality) and resulting binaries execute correctly in a Power8+K40 machine.
Reviewers: echristo, hfinkel, jlebar, ABataev, tra
Subscribers: guansong, andreybokhanko, tcramer, mkuron, cfe-commits, arpith-jacob, carlo.bertolli, caomhin
Differential Revision: https://reviews.llvm.org/D18171
llvm-svn: 275645
Summary: Fix the build to use hasFlag instead of hasArg for checking some flags.
Reviewers: echristo
Subscribers: mehdi_amini, cfe-commits
Differential Revision: http://reviews.llvm.org/D22338
llvm-svn: 275377
Summary:
Depends on D21982 which implements the in-memory logging implementation of the
XRay runtime. These additional changes also depends on D20352 which adds the
bulk of XRay flags/dependencies when using the `-fxray-instrument` flag from
Clang.
Reviewers: echristo, rnk, aaron.ballman
Subscribers: mehdi_amini, cfe-commits
Differential Revision: http://reviews.llvm.org/D21983
llvm-svn: 275368
-fxray-instrument: enables XRay annotation of IR
-fxray-instruction-threshold: configures the threshold for function size (looking at IR instructions), and allow LLVM to decide whether to add the nop sleds later on in the process.
Also implements the related xray_always_instrument and xray_never_instrument function attributes.
Patch by Dean Michael Berris.
llvm-svn: 275330
MASM (ML.exe and ML64.exe) and older versions of MSVC (CL.exe) support a
flag called /Zd which is more-or-less -gline-tables-only.
It seems nicer to support this flag instead of exposing
-gline-tables-only.
llvm-svn: 274991
Add OCL option -cl-no-signed-zeros to driver options.
Also added to opencl.cl testcases.
Patch by Aaron En Ye Shi.
Differential Revision: http://reviews.llvm.org/D22067
llvm-svn: 274923
Summary:
Raise an error if you're using a CUDA installation that's too old for
the requested architectures. In practice, this means that you need a
CUDA 8 install to compile for sm_6*.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21869
llvm-svn: 274781
Summary:
Currently our handling of CUDA architectures is scattered all around
clang. This patch centralizes it.
A key advantage of this centralization is that you can now write a C++
switch on e.g. CudaArch and get a compile error if you don't handle one
of the enum values.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21867
llvm-svn: 274681
Summary: This change exposes the recently added LEON CPUs (D19359) in the LLVM Sparc backend to Clang, allowing the cpu's to be selected using the -mcpu flag.
Reviewers: jyknight, lero_chris
Subscribers: jyknight, cfe-commits
Differential Revision: http://reviews.llvm.org/D21683
llvm-svn: 274487
Allow -cl-std and other standard -cl- options from cc1 to driver.
Added a test for the options moved.
Patch by Aaron En Ye Shi.
Differential Revision: http://reviews.llvm.org/D21031
llvm-svn: 274150
The PIC and PIE levels are not independent. In fact, if PIE is defined
it is always the same as PIC.
This is clear in the driver where ParsePICArgs returns a PIC level and
a IsPIE boolean. Unfortunately that is currently lost and we pass two
redundant levels down the pipeline.
This patch keeps a bool and a PIC level all the way down to codegen.
llvm-svn: 273566
Add support for /Ob1 (and equivalent -finline-hint-functions), which enable
inlining only for functions marked inline, either explicitly (via inline
keyword, for example), or implicitly (function definition in class body,
for example).
This works by enabling inlining pass, and adding noinline attribute to
every function not marked inline.
Patch by Rudy Pons <rudy.pons@ilod.org>!
Differential Revision: http://reviews.llvm.org/D20647
llvm-svn: 273440
Add -mno-iamcu option to:
1) Countervail -miamcu option easily
2) Be compatible with GCC which supports this option
Differential Revision: http://reviews.llvm.org/D21469
llvm-svn: 273147
This mirrors the many other -i*after options to insert a new system search
directory at the end of the search path. This makes it possible to actually
inject a search path after the resource dir. This option is similar in spirit
to the /imsvc option in the clang-cl driver. This is needed to properly use the
driver for Windows targets where the clang headers wrap some of the system
headers.
This concept is actually useful on other targets (e.g. Linux) and would be
really easy to support on the core toolchain.
llvm-svn: 273016
This is the last patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000).
When IAMCU triple is used:
* Use IAMCU linker output format
* Link with IAMCU crt objects
* Link with IAMCU libraries
Differential Revision: http://reviews.llvm.org/D20675
llvm-svn: 272885
This is the second patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000).
When IAMCU triple is used:
* Recognize and use IAMCU GCC toolchain
* Set up include paths
* Forbid C++
Differential Revision: http://reviews.llvm.org/D19274
llvm-svn: 272883
Summary:
This patch introduces the concept of offloading tool chain and offloading kind. Each tool chain may have associated an offloading kind that marks it as used in a given programming model that requires offloading.
It also adds the logic to iterate on the tool chains based on the kind. Currently, only CUDA is supported, but in general a programming model (an offloading kind) may have associated multiple tool chains that require supporting offloading.
This patch does not add tests - its goal is to keep the existing functionality.
This patch is the first of a series of three that attempts to make the current support of CUDA more generic and easier to extend to other programming models, namely OpenMP. It tries to capture the suggestions/improvements/concerns on the initial proposal in http://lists.llvm.org/pipermail/cfe-dev/2016-February/047547.html. It only tackles the more consensual part of the proposal, i.e.does not address the problem of intermediate files bundling yet.
Reviewers: ABataev, jlebar, echristo, hfinkel, tra
Subscribers: guansong, Hahnfeld, andreybokhanko, tcramer, mkuron, cfe-commits, arpith-jacob, carlo.bertolli, caomhin
Differential Revision: http://reviews.llvm.org/D18170
llvm-svn: 272571
GCC still permits enabling the SjLj EH model. This is something which can be
done on various targets. Hoist the -fsjlj-exceptions option into the driver and
pass it through. This allows one to opt into the alternative EH model while
retaining the default to be the target's default.
Resolves PR27749!
llvm-svn: 272424
Summary:
32-bit CPU's default to O32. 64-bit CPU's default to N64. The default CPU
(mips32r2/mips64r2) still depends on the arch so there's no functional
change when the CPU isn't specified but commands like:
clang -target mips-mti-linux-gnu -mips64r2
will now default to a 64-bit ABI like our gcc toolchains do* instead of
asserting in the backend**.
Other vendors (including Triple::UnknownVendor) still derive the default
ABI from the arch.
* Although not the same one as our gcc toolchains, clang has historically
defaulted to N64 where gcc defaults to N32.
** Mixing O32 and a 64-bit CPU causing assertions is a long-standing bug.
Reviewers: atanasyan
Subscribers: sdardis, cfe-commits
Differential Revision: http://reviews.llvm.org/D21016
llvm-svn: 271884
This patch enables +ras +noras to AArch64 in clang.
Patch by: Roger Ferrer Ibanez and Oliver Stannard
Differential Revision: http://reviews.llvm.org/D20283
llvm-svn: 271672
Diagnostics that happen during driver time do not have color output support
unless -fcolor-diagonostic is explicitly passed into the driver. This is not a
problem for cc1 since dianostic arguments are properly handled and color is
enabled by default if the terminal supports it.
Make the driver behave like CC1. There are tests that already check for these
flags, but for the color itself there's no sensible way to test it.
Differential Revision: http://reviews.llvm.org/D20404
rdar://problem/26290980
llvm-svn: 271042
This patch adds the commandline option -mcompact-branches={never,optimal,always),
which controls how LLVM generates compact branches for MIPSR6 targets. By default,
the compact branch policy is 'optimal' where LLVM will generate the most
appropriate branch for any situation. The 'never' and 'always' policy will disable
or always generate compact branches wherever possible respectfully.
Reviewers: dsanders, vkalintiris, atanasyan
Differential Revision: http://reviews.llvm.org/D20729
llvm-svn: 271000
Summary:
There are no llvm backend tests* for EABI and no EABI buildbots. There were only
three clang tests, all of which checked that -mabi=eabi was passed to the
assembler.
*There is a single backend test that specifies EABI but it actually tests MIPS16.
Reviewers: atanasyan
Subscribers: emaste, sdardis, atanasyan, cfe-commits
Differential Revision: http://reviews.llvm.org/D20679
llvm-svn: 270998
OpenMP version.
If '-fopenmp' option is provided '-fopenmp-version=' allows to control,
which version of OpenMP must be supported. Currently it affects only the
value of _OPENMP define.
llvm-svn: 270838
This reverts commit r270688 and r270689. The issue is not a random order, but a
different order for some targets and others (prob. Linux vs Darwin). Reverting until
we have a better fix.
llvm-svn: 270691
Using AArch64TargetParser in clang to avoid repetitive string parsing.
Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation.
Patch by Jojo Ma.
llvm-svn: 270688
-finline-functions and /Ob2 are currently ignored by Clang. The only way to
enable inlining is to use the global O flags, which also enable other options,
or to emit LLVM bitcode using Clang, then running opt by hand with the inline
pass.
This patch allows to simply use the -finline-functions flag (same as GCC) or
/Ob2 in clang-cl mode to enable inlining without other optimizations.
This is the first patch of a serie to improve support for the /Ob flags.
Patch by Rudy Pons <rudy.pons@ilod.org>!
Differential Revision: http://reviews.llvm.org/D20576
llvm-svn: 270609
Summary:
Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option.
The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided.
Reviewers: jyknight, lero_chris
Subscribers: jyknight, cfe-commits
Differential Revision: http://reviews.llvm.org/D20419
llvm-svn: 270538
The parameter already requires the toolchain, sink the method into the class.
This also enables the use of the distro detection logic which will be needed to
support Exherbo's multiarch approach.
llvm-svn: 270352
Convert the cascading if/else to a switch. This makes it easier to follow the
logic. Minor difference is that we no longer default to x86_64 but rather to
the architecture specified by the architecture.
llvm-svn: 270351
licensees actually see in the toolchain we deliver to them. This will
reduce the set of local patches we have to maintain. The triple is
not changing. (The term ORBIS is an internal code name for PS4.)
llvm-svn: 269671
-fms-compatibility-version was defaulting to 18 (VS 2013), which is a pain if your environment is pointing to version 19 (VS 2015) libraries.
If cl.exe can be found, this patch uses its version number as the default instead. It re-uses the existing code to find the Visual Studio binaries folder and WinAPI methods to check its version. You can still explicitly specify a compatibility version on the command line. If you don't have cl.exe, this should be a no-op and you'll get the old default of 18.
This affected the tests, which assumed that if you didn't specific a version, that it would default to 18, but this won't be true for all machines. So a couple test cases had to be eliminated and a couple others had to be tweaked to allow for various outputs.
Addresses: https://llvm.org/bugs/show_bug.cgi?id=27215
Differential Revision: http://reviews.llvm.org/D20136
llvm-svn: 269515
Summary:
This option allows the user to control how much of the file name is
emitted by UBSan. Tuning this option allows one to save space in the
resulting binary, which is helpful for restricted execution
environments.
With a positive N, UBSan skips the first N path components.
With a negative N, UBSan only keeps the last N path components.
Reviewers: rsmith
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D19666
llvm-svn: 269309
Summary:
Teach clang to embed bitcode inside bitcode. When -fembed-bitcode cc1
option is used, clang will embed both the input bitcode and cc1
commandline into the bitcode in special sections before compiling to
the object file. Using -fembed-bitcode-marker will only introduce a
marker in both sections.
Depends on D17390
Reviewers: rsmith
Subscribers: yaron.keren, vsk, cfe-commits
Differential Revision: http://reviews.llvm.org/D17392
llvm-svn: 269202
This patch corresponds to review:
http://reviews.llvm.org/D19684
It simply adds the handling for the option and the corresponding macros.
llvm-svn: 268951
Summary:
Now that LLVM is emitting version 2 of the AMD code object, we can
start using lld again for linking instead of our custom tool.
Reviewers: arsenm, kzhuravl
Subscribers: rafael, cfe-commits
Differential Revision: http://reviews.llvm.org/D19952
llvm-svn: 268648
This option, like the corresponding gcc option, is SystemZ-specific and
enables storing frame backchain links, as specified in the ABI.
Differential Revision: http://reviews.llvm.org/D19891
llvm-svn: 268575
This reverts commit r264813 / 6484b95d634f53dd929c75265ef3c4decf397584.
While using it in the shell is fine, this a problem when cc1as is
invoked directly by the driver because single quoting the clang full
version makes cc1as write out the version with the quotes in the final
binary.
If the user wants to copy-n-pastable output, it could use either -###
or CC_PRINT_OPTIONS=1 clang -v ...
llvm-svn: 268297
It makes compiler-rt tests fail if the gold plugin is enabled.
Revert "Rework interface for bitset-using features to use a notion of LTO visibility."
Revert "Driver: only produce CFI -fvisibility= error when compiling."
Revert "clang/test/CodeGenCXX/cfi-blacklist.cpp: Exclude ms targets. They would be non-cfi."
llvm-svn: 267871
Bitsets, and the compiler features they rely on (vtable opt, CFI),
only have visibility within the LTO'd part of the linkage unit. Therefore,
only enable these features for classes with hidden LTO visibility. This
notion is based on object file visibility or (on Windows)
dllimport/dllexport attributes.
We provide the [[clang::lto_visibility_public]] attribute to override the
compiler's LTO visibility inference in cases where the class is defined
in the non-LTO'd part of the linkage unit, or where the ABI supports
calling classes derived from abstract base classes with hidden visibility
in other linkage units (e.g. COM on Windows).
If the cross-DSO CFI mode is enabled, bitset checks are emitted even for
classes with public LTO visibility, as that mode uses a separate mechanism
to cause bitsets to be exported.
This mechanism replaces the whole-program-vtables blacklist, so remove the
-fwhole-program-vtables-blacklist flag.
Because __declspec(uuid()) now implies [[clang::lto_visibility_public]], the
support for the special attr:uuid blacklist entry is removed.
Differential Revision: http://reviews.llvm.org/D18635
llvm-svn: 267784
Summary:
Adds a framework to enable the instrumentation pass for the new
EfficiencySanitizer ("esan") family of tools. Adds a flag for esan's
cache fragmentation tool via -fsanitize=efficiency-cache-frag.
Adds appropriate tests for the new flag.
Reviewers: eugenis, vitalybuka, aizatsky, filcab
Subscribers: filcab, kubabrecka, llvm-commits, zhaoqin, kcc
Differential Revision: http://reviews.llvm.org/D19169
llvm-svn: 267059
We've already paid the price for separate "armv7m" and "armv7em" slices
(support in other tools), it's silly to make them identical other than the
default CPU.
rdar://23055688
llvm-svn: 266211
FreeBSD uses LLVM's libunwind on FreeBSD/arm64 today (and is expected to
use it more widely in the future), and it requires the EH frame segment
in static binaries.
This is the same as r203742 for NetBSD.
Differential Revision: http://reviews.llvm.org/D19029
llvm-svn: 266123
This is the clang part of http://reviews.llvm.org/D18846.
SafeStack instrumentation pass adds stack protector canaries if both
attributes are present on a function. StackProtector pass will step
back if the function has a safestack attribute.
llvm-svn: 266005
As we're currently working on making CloudABI executables easier to
emulate in userspace (e.g., on OS X and Windows), it makes a whole lot
of sense to build these using PIE. By using PIE, they can simply be
loaded into the existing process address space without clashes.
PIE support got added to CloudABI's C library and seems to work pretty
well. CloudABI does not make use of an ld.so, so the binary's _start()
has all the logic in it to do the relocations.
Now that all but one bug in LLD relating to PIE support have been
squashed (and a patch for that is already in code review), I'd like to
go ahead and force the use of PIE for Clang 3.9. When released, we'll
also switch over to using LLD exclusively.
llvm-svn: 265546
Add no-jump-tables flag to disable use of jump tables when lowering
switch statements
Reviewers: echristo, hans
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D18407
llvm-svn: 265425
Summary:
* -fcuda-target-overloads
Previously unconditionally set to true by the driver. Necessary for
correct functioning of the compiler -- our CUDA headers wrapper won't
compile without this.
* -fcuda-disable-target-call-checks
Previously unconditionally set to true by the driver. Necessary to
compile almost any external CUDA code -- almost all libraries assume
that host+device code can call host or device functions.
* -fcuda-allow-host-calls-from-host-device
No effect when target overloading is enabled.
Reviewers: tra
Subscribers: rsmith, cfe-commits
Differential Revision: http://reviews.llvm.org/D18416
llvm-svn: 264739
Most things even work; see the included FIXMEs for things that need polishing.
Also don't warn about unused flags for the `/Yuh2.h /FIh1.h /FIh2.h`. The
common case is that the pch was built with `/Ych2.h /FIh1.h /FIh2.h`, so h1.h
is in the PCH, and we shouldn't warn about /FIh1.h not having an effect.
(If we wanted to get fancy, we could store the list of -include flags in the
pch and then check that it matches later on.)
llvm-svn: 264178
This reverts commit r263607.
This change caused more objc_retain/objc_release calls in the IR but those
are then incorrectly optimized by the ARC optimizer. Work is going to have
to be done to ensure the ARC optimizer doesn't optimize user written RR, but
that should land before this change.
This change will also need to be updated to take account for any changes required
to ensure that user written calls to RR are distinct from those inserted by ARC.
llvm-svn: 263984
It is faster to directly call the ObjC runtime for methods such as retain/release instead of sending a message to those functions.
This patch adds support for converting messages to retain/release/alloc/autorelease to their equivalent runtime calls.
Tests included for the positive case of applying this transformation, negative tests that we ensure we only convert "alloc" to objc_alloc, not "alloc2", and also a driver test to ensure we enable this only for supported runtime versions.
Reviewed by John McCall.
Differential Revision: http://reviews.llvm.org/D14737
llvm-svn: 263607
This enables "--rtlib compiler-rt" option under MSVC environment.
Patch by Roman Shirokiy.
Differential Revision: http://reviews.llvm.org/D17453
llvm-svn: 263422
Summary:
This flag is enabled by default in the driver when NDEBUG is set. It
is forwarded on the LLVMContext to discard all value names (but
GlobalValue) for performance purpose.
This an improved version of D18024
Reviewers: echristo, chandlerc
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D18127
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 263394
Summary:
Using -no-integrated-as causes -mcpu=krait to be transformed into
-march=armv7-a today. This precludes the assembler from using
instructions like sdiv, which are present for krait. Cortex-a15 is the
closest subset of functionality for krait, so we should switch the
assembler to use that instead.
Reviewers: cfe-commits, apazos, weimingz
Subscribers: aemerson
Differential Revision: http://reviews.llvm.org/D17874
llvm-svn: 262742
Sean Silva