a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
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llvm-svn: 145510
2011-11-30 19:35:44 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
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llvm-svn: 145450
2011-11-29 22:58:48 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
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llvm-svn: 145442
2011-11-29 22:38:04 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
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llvm-svn: 145420
2011-11-29 19:25:30 +00:00
05060f0748
Fix a misplaced paren bug.
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llvm-svn: 144692
2011-11-15 20:30:41 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
52823cc91c
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
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- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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llvm-svn: 144384
2011-11-11 12:39:41 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
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llvm-svn: 143634
2011-11-03 18:53:17 +00:00
ec5c5f7008
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
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llvm-svn: 143553
2011-11-02 17:46:18 +00:00
fad59dab62
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
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llvm-svn: 143552
2011-11-02 17:41:23 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
8a6ebd085a
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
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llvm-svn: 143162
2011-10-27 22:53:10 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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llvm-svn: 142817
2011-10-24 18:04:29 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
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llvm-svn: 142726
2011-10-22 16:50:00 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
79ebc51c45
Tidy up. Trailing whitespace.
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llvm-svn: 142591
2011-10-20 17:28:20 +00:00
34957911e7
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
8b478360ef
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
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llvm-svn: 141914
2011-10-13 23:36:06 +00:00
44f76eafae
SETEND is not allowed in an IT block.
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llvm-svn: 141874
2011-10-13 17:58:39 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
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The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
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llvm-svn: 141794
2011-10-12 18:11:24 +00:00
6a5c150e9c
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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llvm-svn: 141339
2011-10-06 23:33:11 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
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llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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llvm-svn: 140412
2011-09-23 21:00:32 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
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llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
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llvm-svn: 140102
2011-09-19 23:47:10 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
...
llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
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llvm-svn: 139969
2011-09-16 23:04:48 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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llvm-svn: 139964
2011-09-16 22:29:48 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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llvm-svn: 139943
2011-09-16 21:08:33 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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llvm-svn: 139876
2011-09-15 23:38:46 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
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llvm-svn: 139736
2011-09-14 21:06:21 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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llvm-svn: 139381
2011-09-09 18:37:27 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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llvm-svn: 139268
2011-09-08 00:11:18 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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llvm-svn: 139237
2011-09-07 17:24:38 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
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llvm-svn: 138948
2011-09-01 18:02:14 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
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llvm-svn: 138910
2011-08-31 22:00:41 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
...
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
d14b70d00b
Tidy up. 80 columns.
...
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
...
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
...
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
...
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
...
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
...
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
...
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
...
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
...
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
...
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
...
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
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llvm-svn: 137337
2011-08-11 20:04:56 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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llvm-svn: 137320
2011-08-11 18:24:51 +00:00
d5d6359785
ARM LDRT assembly parsing and encoding.
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llvm-svn: 137282
2011-08-10 23:43:54 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
5d69f63bbb
Cleanups based on Nick Lewycky's feedback.
...
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
d151b09921
Silence an false-positive warning.
...
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
a70fbfd577
ARM simplify the postidx_reg operand encoding.
...
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
llvm-svn: 136969
2011-08-05 16:11:38 +00:00
08d4bb0f12
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
...
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
c4dc52cd52
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
9d7feab3e0
Rewrite the CMake build to use explicit dependencies between libraries,
...
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.
I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.
This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.
This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.
Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.
This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.
llvm-svn: 136433
2011-07-29 00:14:25 +00:00
b0e6899398
Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
...
llvm-svn: 136362
2011-07-28 17:18:57 +00:00
b81af2abe0
Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
...
llvm-svn: 136295
2011-07-27 23:36:57 +00:00
03f56d9de6
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
d2659138da
ARM cleanup of rot_imm encoding.
...
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
llvm-svn: 136152
2011-07-26 21:28:43 +00:00
97c069c1d2
Clean up a pile of hacks in our CMake build relating to TableGen.
...
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.
These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.
To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.
This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.
Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.
llvm-svn: 136023
2011-07-26 00:09:08 +00:00
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
801e0a3fde
ARM SSAT instruction 5-bit immediate handling.
...
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
2011-07-22 23:16:18 +00:00
39f9388a9d
Thumb assembly support for SETEND instruction.
...
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
0491270f99
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
...
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
...
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
a288b1c10a
ARM PKH shift ammount operand printing tweaks.
...
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
2011-07-20 21:40:26 +00:00
a98f80095b
ARM: Tidy up representation of PKH instruction.
...
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
llvm-svn: 135616
2011-07-20 20:32:09 +00:00
83c6c4f30e
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
...
llvm-svn: 135442
2011-07-18 23:25:34 +00:00
64d53620aa
Re-apply r135319 with a fix for the constant island pass.
...
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135414
2011-07-18 18:50:52 +00:00
2ebff84b90
Revert r135319 in an attempt to get to unbreak testers.
...
llvm-svn: 135343
2011-07-16 09:17:43 +00:00
d57a049e5c
Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
...
llvm-svn: 135319
2011-07-15 22:49:31 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
cb1a888fde
Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
...
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.
llvm-svn: 135269
2011-07-15 12:50:21 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
...
registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
b218202586
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
1e210d08d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
...
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
...
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
a51604e511
Restore an accidentally removed comment.
...
llvm-svn: 132044
2011-05-25 04:48:17 +00:00
310b3472ec
Change the order of tBX's operands so that the predicate operands come after the
...
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
llvm-svn: 132041
2011-05-25 04:45:23 +00:00
012247e60c
Rename tBX_Rm to tBX.
...
llvm-svn: 132040
2011-05-25 04:45:20 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
llvm-svn: 131565
2011-05-18 20:32:41 +00:00
886894cb70
Fix a bug in the case that there is no add or subtract symbol and the offset
...
value is zero so it does not add a NULL expr operand.
llvm-svn: 130330
2011-04-27 21:02:27 +00:00
dc62e59776
Fix typo in the comment.
...
llvm-svn: 129837
2011-04-19 23:58:52 +00:00
48592ee5af
Thumb2 BFC was insufficiently encoded.
...
rdar://problem/9292717
llvm-svn: 129619
2011-04-15 22:52:15 +00:00
761e1e3512
A8.6.315 VLD3 (single 3-element structure to all lanes)
...
The a bit must be encoded as 0.
rdar://problem/9292625
llvm-svn: 129618
2011-04-15 22:49:08 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
...
(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
...
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
...
rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
...
rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
...
rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
70591cbc60
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
...
rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
0d306a7840
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
...
rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
3c2f74c9f3
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
...
rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
960eef3db3
The Thumb2 RFE instructions need to have their second halfword fully specified.
...
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
01637b9acb
Add bad register checks for Thumb2 Ld/St instructions.
...
rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
ab86a519f8
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
...
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
d0e2be39ea
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
...
llvm-svn: 129365
2011-04-12 17:09:04 +00:00
672ef14a62
A8.6.16 B
...
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f79d5365de
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
...
rdar://problem/9266265
llvm-svn: 129298
2011-04-11 21:14:35 +00:00
74adbddade
Trivial comment fix.
...
llvm-svn: 129288
2011-04-11 18:51:50 +00:00
66fab75920
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
...
invalid instructions.
llvm-svn: 129286
2011-04-11 18:34:12 +00:00
9377a52c12
Adding support for printing operands symbolically to llvm's public 'C'
...
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 129284
2011-04-11 18:08:50 +00:00
4e1796e8d1
Fix an apparent typo that made GCC complain
...
llvm-svn: 129160
2011-04-08 21:59:49 +00:00
f2faf4e53a
Check opcoe (dmb, dsb) instead of bitfields matching.
...
llvm-svn: 129148
2011-04-08 20:03:46 +00:00
a9570f77d5
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
...
PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
875e0e4626
Sanity check the option operand for DMB/DSB.
...
PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
...
Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
07606661f9
Add sanity checking for invalid register encodings for saturating instructions.
...
llvm-svn: 129096
2011-04-07 19:02:08 +00:00
194a2267ad
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
313ec7953a
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
c0e86fb965
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
d4cced54b3
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
llvm-svn: 129042
2011-04-07 00:50:25 +00:00
bd9a4f8d07
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
llvm-svn: 129033
2011-04-06 22:14:48 +00:00
2ac486e387
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
2011-04-06 20:49:02 +00:00
8bca174f48
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
0ec0e98a6a
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
...
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
2011-04-06 01:18:32 +00:00
f6e327c6a3
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Jim Grosbach