Commit Graph

181 Commits

Author SHA1 Message Date
Krzysztof Parzyszek a696b1b641 [Hexagon] Expand sext- and zextloads of vector types, not just extloads
Recent change exposed this issue, breaking the Hexagon buildbots.

llvm-svn: 280973
2016-09-08 17:42:14 +00:00
Krzysztof Parzyszek fb4c4178a2 [Hexagon] Fix subesthetic indentation
llvm-svn: 279303
2016-08-19 19:29:15 +00:00
Krzysztof Parzyszek 505eb498bd [Hexagon] Allow i1 values for 'r' constraint in inline-asm
llvm-svn: 279302
2016-08-19 19:17:28 +00:00
Krzysztof Parzyszek 8849a51370 [Hexagon] Do not cache alloca instructions during isel
They can be deleted or replicated, so the cache may become outdated.
They only need to be visited once during frame lowering, so just scan
the function instead.

llvm-svn: 279297
2016-08-19 18:46:13 +00:00
Krzysztof Parzyszek 0ba9754584 [Hexagon] Allow tail-call optimization when mixing C and fast calling conv
Patch by Arnold Schwaighofer.

llvm-svn: 279251
2016-08-19 15:02:18 +00:00
Krzysztof Parzyszek bd8ef4b8ce [Hexagon] Improvements to handling and generation of FP instructions
Improved handling of fma, floating point min/max, additional load/store
instructions for floating point types.

Patch by Jyotsna Verma.

llvm-svn: 279239
2016-08-19 13:34:31 +00:00
Michael Kuperstein 2bc3d4d46c [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround
The names of the tablegen defs now match the names of the ISD nodes.
This makes the world a slightly saner place, as previously "fround" matched
ISD::FP_ROUND and not ISD::FROUND.

Differential Revision: https://reviews.llvm.org/D23597

llvm-svn: 279129
2016-08-18 20:08:15 +00:00
Krzysztof Parzyszek 1d01a79304 [Hexagon] Standardize next batch of pseudo instructions
ALIGNA          PS_aligna
ALLOCA          PS_alloca
TFR_FI          PS_fi
TFR_FIA         PS_fia
TFR_PdFalse     PS_false
TFR_PdTrue      PS_true
VMULW           PS_vmulw
VMULW_ACC       PS_vmulw_acc

llvm-svn: 278832
2016-08-16 18:08:40 +00:00
Ron Lieberman 822ee88ab8 Fix unsupported relocation type R_HEX_6_X' for symbol .rodata
LowerTargetConstantPool is not properly setting the TargetFlag to indicate
desired relocation. Coding error, the offset parameter was omitted, so the
TargetFlag was used as the offset, and the TargetFlag defaulted to zero.

This only affects -fpic compilation, and only those items created in a
Constant Pool, for example a vector of constants. Halide ran into this issue.

llvm-svn: 278614
2016-08-13 23:41:11 +00:00
Krzysztof Parzyszek be976d4ea9 [Hexagon] Standardize pseudo-instructions for calls and returns
- CALLv3nr        PS_call_nr
- CALLRv3nr       PS_callr_nr
- CALLstk         PS_call_stk

- TCRETURNi       PS_tailcall_i
- TCRETURNr       PS_tailcall_r

- JMPret          PS_jmpret
- JMPrett         PS_jmprett
- JMPretf         PS_jmpretf
- JMPrettnew      PS_jmprettnew
- JMPretfnew      PS_jmpretfnew
- JMPrettnewpt    PS_jmprettnewpt
- JMPretfnewpt    PS_jmpretfnewpt

llvm-svn: 278499
2016-08-12 11:12:02 +00:00
Krzysztof Parzyszek 2a48ce4ec2 [Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32
llvm-svn: 278236
2016-08-10 16:20:33 +00:00
Krzysztof Parzyszek 341cf3fbe5 [Hexagon] Add pattern for 64-bit mulhs
llvm-svn: 278040
2016-08-08 19:24:25 +00:00
Krzysztof Parzyszek ed4e7827bb [Hexagon] Do not check alignment for unsized types in isLegalAddressingMode
When the same base address is used to load two different data types, LSR
would assume a memory type of "void". This type is not sized and has no
alignment information. Checking for it causes a crash.

llvm-svn: 277601
2016-08-03 15:06:18 +00:00
Krzysztof Parzyszek 3e409e127e [Hexagon] Improvements to address mode checks in TargetLowering
- Implement getOptimalMemOpType.
- Check BaseOffset in isLegalAddressingMode.

llvm-svn: 277494
2016-08-02 18:34:31 +00:00
Krzysztof Parzyszek 317d42c1ea [Hexagon] Tidy up some code, NFC: reapply r277372 with a fix
llvm-svn: 277383
2016-08-01 20:31:50 +00:00
Krzysztof Parzyszek d978ae239e Revert r277372, it is causing buildbot failures
llvm-svn: 277374
2016-08-01 20:00:33 +00:00
Krzysztof Parzyszek 1f72abb56b [Hexagon] Tidy up some code, NFC
llvm-svn: 277372
2016-08-01 19:46:21 +00:00
Krzysztof Parzyszek 3e137e3429 Revert r277178, the actual change had already been applied
Will submit another patch with the testcase only.

llvm-svn: 277180
2016-07-29 17:50:47 +00:00
Krzysztof Parzyszek 68fe439d06 [Hexagon] Misaligned loads and stores are not fast
The DAG combiner tries to merge stores to adjacent vector wide memory
locations by creating stores which are integral multiples of the vector
width. Discourage this by informing it that this is slow. This should
not affect legalization passes, because all of them ignore the "Fast"
argument.

Patch by Pranav Bhandarkar.

llvm-svn: 277178
2016-07-29 17:45:16 +00:00
Krzysztof Parzyszek 0bd55a7608 [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
If the mask of a vector shuffle has alternating odd or even numbers
starting with 1 or 0 respectively up to the largest possible index
for the given type in the given HVX mode (single of double) we can
generate vpacko or vpacke instruction respectively.

E.g.
  %42 = shufflevector <32 x i16> %37, <32 x i16> %41,
                      <32 x i32> <i32 1, i32 3, ..., i32 63>
  is %42.h = vpacko(%41.w, %37.w)

Patch by Pranav Bhandarkar.

llvm-svn: 277168
2016-07-29 16:44:27 +00:00
Matthias Braun 941a705b7b MachineFunction: Return reference for getFrameInfo(); NFC
getFrameInfo() never returns nullptr so we should use a reference
instead of a pointer.

llvm-svn: 277017
2016-07-28 18:40:00 +00:00
Krzysztof Parzyszek 2a480599bb [Hexagon] Post-increment loads/stores enhancements
- Generate vector post-increment stores more aggressively.
- Predicate post-increment and vector stores in early if-conversion.

llvm-svn: 276800
2016-07-26 20:30:30 +00:00
Krzysztof Parzyszek 080bebd212 [Hexagon] Add target feature to generate long calls
llvm-svn: 276638
2016-07-25 14:42:11 +00:00
Krzysztof Parzyszek 14412ef07a [Hexagon] Handle returning small structures by value
This is not compliant with the official ABI, but allows experimentation
with calling conventions.

llvm-svn: 275825
2016-07-18 17:36:46 +00:00
Krzysztof Parzyszek 4661a958d8 [Hexagon] Revert r275822: mistake in commit message
llvm-svn: 275824
2016-07-18 17:34:49 +00:00
Krzysztof Parzyszek 5948ea78b9 [Hexagon] Handle returning small structures by value
This is compliant with the official ABI, but allows experimentation with
calling conventions.

llvm-svn: 275822
2016-07-18 17:30:41 +00:00
Justin Lebar 9c375817ac [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).

Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.

This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted.  It also greatly simplifies the process of adding another flag
to getLoad.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits

Differential Revision: http://reviews.llvm.org/D22249

llvm-svn: 275592
2016-07-15 18:27:10 +00:00
Duncan P. N. Exon Smith e4f5e4f4d1 CodeGen: Use MachineInstr& in TargetLowering, NFC
This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr.  In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

llvm-svn: 274287
2016-06-30 22:52:52 +00:00
Rafael Espindola db6bd02185 Delete unused includes. NFC.
llvm-svn: 274225
2016-06-30 12:19:16 +00:00
Rafael Espindola 3beef8d6db Move shouldAssumeDSOLocal to Target.
Should fix the shared library build.

llvm-svn: 273958
2016-06-27 23:15:57 +00:00
Rafael Espindola 405e25a970 Use isPositionIndependent predicate. NFC.
llvm-svn: 273827
2016-06-26 22:24:01 +00:00
Nirav Dave bfdb483755 Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after correcting over-eager Debug Value transfer fixing PR28270.

[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

llvm-svn: 273585
2016-06-23 17:52:57 +00:00
Peter Collingbourne 6717803485 Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as it caused pr28270.
llvm-svn: 273518
2016-06-23 00:06:17 +00:00
Rafael Espindola 8474fdf90d Start using shouldAssumeDSOLocal on Hexagon.
Include a token test showing that access to private is now the same as
to internal.

llvm-svn: 273457
2016-06-22 19:09:14 +00:00
Nirav Dave 96beb7dee5 Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after fixing over-aggressive assertion

[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

llvm-svn: 273456
2016-06-22 19:03:26 +00:00
Krzysztof Parzyszek f228c95f87 [Hexagon] Handle expansion of cmpxchg
llvm-svn: 273432
2016-06-22 16:07:10 +00:00
Nirav Dave 194cb55f37 Revert "Preserve DebugInfo when replacing values in DAGCombiner"
Reverting due to assertion failure in
lib/CodeGen/SelectionDAG/InstrEmitter.cpp

This reverts commit r272792.

llvm-svn: 272799
2016-06-15 16:08:50 +00:00
Nirav Dave a72e308403 Preserve DebugInfo when replacing values in DAGCombiner
[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

llvm-svn: 272792
2016-06-15 14:50:08 +00:00
Benjamin Kramer bdc4956bac Pass DebugLoc and SDLoc by const ref.
This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.

llvm-svn: 272512
2016-06-12 15:39:02 +00:00
Krzysztof Parzyszek ca3b532e2c [Hexagon] Recognize "q" and "v" in inline-asm as register constraints
llvm-svn: 269933
2016-05-18 14:34:51 +00:00
Craig Topper 33772c5375 [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior.
llvm-svn: 267853
2016-04-28 03:34:31 +00:00
Craig Topper 6e6a1f0a5b [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC
llvm-svn: 267266
2016-04-23 02:49:31 +00:00
Krzysztof Parzyszek 5de5910d7d [Hexagon] Expand handling of the small-data/bss section
llvm-svn: 267034
2016-04-21 18:56:45 +00:00
Craig Topper 18e69f4f63 Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.
llvm-svn: 266414
2016-04-15 06:20:21 +00:00
Krzysztof Parzyszek 2d65ea74dc [Hexagon] Improve handling of unaligned vector loads and stores
llvm-svn: 264584
2016-03-28 15:43:03 +00:00
James Y Knight f44fc5219f Tweak some atomics functions in preparation for larger changes; NFC.
- Rename getATOMIC to getSYNC, as llvm will soon be able to emit both
  '__sync' libcalls and '__atomic' libcalls, and this function is for
  the '__sync' ones.

- getInsertFencesForAtomic() has been replaced with
  shouldInsertFencesForAtomic(Instruction), so that the decision can be
  made per-instruction. This functionality will be used soon.

- emitLeadingFence/emitTrailingFence are no longer called if
  shouldInsertFencesForAtomic returns false, and thus don't need to
  check the condition themselves.

llvm-svn: 263665
2016-03-16 22:12:04 +00:00
Sanjay Patel 7506852709 [DAG] use !isUndef() ; NFCI
llvm-svn: 263453
2016-03-14 18:09:43 +00:00
Sanjay Patel 5719584129 [DAG] use isUndef() ; NFCI
llvm-svn: 263448
2016-03-14 17:28:46 +00:00
Krzysztof Parzyszek 51155fc0d1 [Hexagon] Fix lowering of calls with the return type of i1
This fixes an assertion in test/CodeGen/Hexagon/ifcvt-edge-weight.ll
when run with -debug-only=isel

llvm-svn: 262726
2016-03-04 17:38:05 +00:00
Krzysztof Parzyszek 7a737d1abb [Hexagon] Implement TLS support
Patch by Anand Kodnani.

llvm-svn: 261218
2016-02-18 15:42:57 +00:00