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92 Commits

Author SHA1 Message Date
Justin Bogner cd1d5aaf2e Replace a few more "fall through" comments with LLVM_FALLTHROUGH 
Follow up to r278902. I had missed "fall through", with a space.

llvm-svn: 278970
 2016-08-17 20:30:52 +00:00
Craig Topper 6189d3ecd4 [X86] Rename VINSERTzrr to use a capital Z to match other instructions. NFC 
llvm-svn: 275939
 2016-07-19 01:26:19 +00:00
Simon Pilgrim a76a8e50e5 [X86][AVX] Add VBROADCASTF128/VBROADCASTI128 shuffle comments support 
llvm-svn: 275400
 2016-07-14 12:07:43 +00:00
Simon Pilgrim 68ea80649b [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle comments 
llvm-svn: 274469
 2016-07-03 18:40:24 +00:00
Simon Pilgrim a0d73835b2 [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQ 
llvm-svn: 274468
 2016-07-03 18:27:37 +00:00
Simon Pilgrim 5080e7f56c [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specific 
llvm-svn: 274467
 2016-07-03 18:02:43 +00:00
Simon Pilgrim dbd6db0dc7 [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle comments 
llvm-svn: 274466
 2016-07-03 15:00:51 +00:00
Simon Pilgrim 598bdb6bfe [X86][AVX512] Add support for UNPCK masked shuffle comments 
llvm-svn: 274464
 2016-07-03 14:26:21 +00:00
Simon Pilgrim 1f59076196 [X86][AVX512] Add support for VPERM/VSHUF masked shuffle comments 
llvm-svn: 274462
 2016-07-03 13:55:41 +00:00
Simon Pilgrim 68f438a036 [X86][AVX512] Add support for PMOVZX masked shuffle comments 
llvm-svn: 274461
 2016-07-03 13:33:28 +00:00
Simon Pilgrim 7c2fbdc101 [X86][AVX512] Add support for masked shuffle comments 
This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments.

This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course.

Differential Revision: http://reviews.llvm.org/D21953

llvm-svn: 274459
 2016-07-03 13:08:29 +00:00
Simon Pilgrim d386941676 [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment generation 
Now matches other shuffles

llvm-svn: 272464
 2016-06-11 11:18:38 +00:00
Craig Topper 200d237e57 [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ. 
llvm-svn: 272371
 2016-06-10 05:12:40 +00:00
Craig Topper 89c1761474 [AVX512] Fix shuffle comment printing to handle the masked versions of some shuffles. Previously we were printing the mask operands as the register names. 
llvm-svn: 272367
 2016-06-10 04:48:05 +00:00
Simon Pilgrim 643734c565 [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction comments 
llvm-svn: 272319
 2016-06-09 22:03:15 +00:00
Craig Topper 6f7288dc44 [AVX512] Fix shuffle decode printing for several instructions with write masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. 
llvm-svn: 272252
 2016-06-09 07:49:08 +00:00
Craig Topper 7a2993093e [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. 
llvm-svn: 272249
 2016-06-09 07:06:38 +00:00
Craig Topper 01f53b1773 [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW. 
llvm-svn: 271628
 2016-06-03 05:31:00 +00:00
Craig Topper 22ae353207 [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. 
llvm-svn: 270317
 2016-05-21 06:07:18 +00:00
Simon Pilgrim 6ce35dd9ea [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments. 
Fixed incorrect operands indices used to access src registers

llvm-svn: 269221
 2016-05-11 18:53:44 +00:00
Simon Pilgrim 3016d9e9e1 [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI. 
llvm-svn: 269209
 2016-05-11 17:36:32 +00:00
Simon Pilgrim 41c05c019e [X86][AVX512] Updated shuffle comments instruction macros to split writemask instructions. NFC 
This will make it easier to support the different writemask cases in shuffle comments

llvm-svn: 269174
 2016-05-11 11:55:12 +00:00
Simon Pilgrim af742d51ad [X86][SSE] Added TODO comment to add support for AVX512 mask registers to shuffle comments 
This came up in discussion on D19198

llvm-svn: 268915
 2016-05-09 13:30:16 +00:00
Simon Pilgrim a3d674470c [X86][SSE] Added support for MOVHPD/MOVLPD + MOVHPS/MOVLPS shuffle decoding. 
llvm-svn: 260034
 2016-02-07 15:39:22 +00:00
Simon Pilgrim 0acc32a3b3 [X86][AVX512] Added support for VPMOVZX shuffle decoding. 
llvm-svn: 260007
 2016-02-06 19:51:21 +00:00
Simon Pilgrim bfa5f236e4 [X86][SSE] Moved shuffle decode CASE macros earlier. NFC. 
To allow the helper functions to make use of them.

llvm-svn: 259997
 2016-02-06 17:02:15 +00:00
Simon Pilgrim e1b6db901f [X86][SSE] Refactored PMOVZX shuffle decoding to use scalar input types 
First step towards being able to decode AVX512 PMOVZX instructions without a massive bloat in the shuffle decode switch statement.

This should also make it easier to decode X86ISD::VZEXT target shuffles in the future.

llvm-svn: 259995
 2016-02-06 16:33:42 +00:00
Simon Pilgrim 96fe4ef5f7 [X86][AVX512] Add support for AVX512 VMOVQ (load) shuffle decoding 
llvm-svn: 259496
 2016-02-02 13:32:56 +00:00
Simon Pilgrim 5be17b6e3e [X86][AVX512] Add support for AVX512 VMOVD (load) shuffle decoding 
llvm-svn: 259430
 2016-02-01 23:04:05 +00:00
Simon Pilgrim f5c23ad3d7 [X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decoding 
llvm-svn: 259427
 2016-02-01 22:26:28 +00:00
Simon Pilgrim 025a3d857a [X86][AVX512] Add support for AVX512 VINSERTPS shuffle decoding 
llvm-svn: 259420
 2016-02-01 22:05:50 +00:00
Craig Topper 74658dfaad [X86] Remove a return after llvm_unreachable. 
llvm-svn: 256681
 2015-12-31 22:40:48 +00:00
Simon Pilgrim 3e0c022aed Fix line endings 
llvm-svn: 255459
 2015-12-13 12:49:48 +00:00
Simon Pilgrim 052191dd82 [X86][AVX512] Added support for VMOVQ shuffle comments 
llvm-svn: 255442
 2015-12-12 21:46:23 +00:00
Simon Pilgrim d5a154424b [X86][AVX512] Added AVX512 VMOVLHPS/VMOVHLPS shuffle decode comments. 
llvm-svn: 253777
 2015-11-21 13:04:42 +00:00
Igor Breger 1f78296869 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
 2015-11-19 08:26:56 +00:00
Simon Pilgrim 2da4178737 [X86][AVX512] Added AVX512 SHUFP*/VPERMILP* shuffle decode comments. 
llvm-svn: 253396
 2015-11-17 23:29:49 +00:00
Simon Pilgrim 8483df6e24 [X86][AVX512] Added support for AVX512 UNPCK shuffle decode comments. 
llvm-svn: 253391
 2015-11-17 22:35:45 +00:00
Simon Pilgrim 13d3a20ad7 [X86][SSE] Merged BLEND shuffle decode comments. NFC. 
Now that we can recognise different vector sizes.

llvm-svn: 253268
 2015-11-16 23:03:18 +00:00
Simon Pilgrim b9ada27052 [X86][SSE] Merged ALIGNR/SLLDQ/SRLDQ shuffle decode comments. NFC. 
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

llvm-svn: 253266
 2015-11-16 22:54:41 +00:00
Simon Pilgrim 5883a73f18 [X86][SSE] Merged SHUF/PERM shuffle decode comments. NFC. 
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

llvm-svn: 253260
 2015-11-16 22:39:27 +00:00
Simon Pilgrim 66e43ee289 [X86][SSE] Merged UNPCK shuffle decode comments. NFC. 
Now that we can recognise different vector sizes - will make future AVX512 additions easier.

llvm-svn: 253258
 2015-11-16 22:21:10 +00:00
Igor Breger 24cab0fa06 AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253185
 2015-11-16 07:22:00 +00:00
Igor Breger 3ff8ef9eb7 Revert r253160. 
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.

llvm-svn: 253163
 2015-11-15 12:19:11 +00:00
Igor Breger aa40ddd3ba AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253160
 2015-11-15 07:23:13 +00:00
Igor Breger d7bae451de AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( shuffle packed values at 128-bit granularity ) 
Differential Revision: http://reviews.llvm.org/D13648

llvm-svn: 250400
 2015-10-15 13:29:07 +00:00
Simon Pilgrim f8f86ab176 [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles. 
Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles.
Added shuffle decodes for 3DNow! PSWAPD shuffles.

llvm-svn: 247526
 2015-09-13 11:28:45 +00:00
Simon Pilgrim d85cae3d52 [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructions 
This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it.

As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions.

From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level.

Differential Revision: http://reviews.llvm.org/D10146

llvm-svn: 241508
 2015-07-06 20:46:41 +00:00
NAKAMURA Takumi 5582a6a4a5 Reformat. 
llvm-svn: 238126
 2015-05-25 01:43:34 +00:00
NAKAMURA Takumi fb3bd7127a Prune CRLFs. 
llvm-svn: 238125
 2015-05-25 01:43:23 +00:00