d3ccf00870
INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
...
cause performance degradation.
llvm-svn: 42653
2007-10-05 21:55:32 +00:00
fa2c828687
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
...
leal 1(%ecx), %edi, which requires 67H prefix.
llvm-svn: 42647
2007-10-05 20:34:26 +00:00
aac0f8e351
Add support to convert more 64-bit instructions to 3-address instructions.
...
llvm-svn: 42642
2007-10-05 18:20:36 +00:00
a8a9c15e30
Testing convertToThreeeAddress as X86 llcbeta.
...
llvm-svn: 42630
2007-10-05 08:04:01 +00:00
5fb5a1f389
Enabling new condition code modeling scheme.
...
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
e95f391ef1
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
...
all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
3243e10ef0
Add 64-bit jmp instructions to the list of instructions that
...
can terminate a block with no fall-through.
llvm-svn: 42029
2007-09-17 15:19:08 +00:00
48ea03d169
Add patterns for SHLD64* and SHRD64*.
...
llvm-svn: 41975
2007-09-14 23:17:45 +00:00
483e1ce16e
Add implicit def of EFLAGS on those instructions that may modify flags.
...
llvm-svn: 41962
2007-09-14 21:48:26 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
189df733ed
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:
...
leal (,%rcx,8), %rcx
It should be
leal (,%rcx,8), %ecx
llvm-svn: 41735
2007-09-06 00:14:41 +00:00
d36d30b53c
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.
...
llvm-svn: 41007
2007-08-10 21:18:25 +00:00
936d17aa1b
Don't pollute the meaning of isUnpredicatedTerminator.
...
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
...
llvm-svn: 37960
2007-07-06 23:22:03 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
...
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
e2324ca17d
Remove some invalid instructions from this check.
...
llvm-svn: 36404
2007-04-24 21:17:46 +00:00
ac5b650a54
Adding more MMX instructions.
...
llvm-svn: 35638
2007-04-03 23:48:32 +00:00
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
...
llvm-svn: 35616
2007-04-03 06:00:37 +00:00
bcd38852f2
Compile CodeGen/X86/lea-3.ll:test2 to:
...
_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret
instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret
llvm-svn: 35434
2007-03-28 18:12:31 +00:00
c56e4920d2
Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the
...
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".
llvm-svn: 35393
2007-03-28 00:58:40 +00:00
3e1d917e80
Two changes:
...
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2 , #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
llvm-svn: 35204
2007-03-20 06:08:29 +00:00
6092ce25cf
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
...
moves, loads, etc. are recognized.
llvm-svn: 35031
2007-03-08 22:09:11 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
07fc107e90
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.
...
llvm-svn: 32097
2006-12-01 21:52:41 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
7ae482c52a
Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.
...
llvm-svn: 31794
2006-11-16 23:22:26 +00:00
dc2c8748a7
Properly transfer kill / dead info.
...
llvm-svn: 31765
2006-11-15 20:58:11 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
7443600ef8
fix wonky indentation
...
llvm-svn: 31298
2006-10-30 22:27:23 +00:00
53ebf20c26
add another target hook for branch folding.
...
llvm-svn: 31262
2006-10-28 17:29:57 +00:00
3a897f31fa
Implement support for branch condition reversal.
...
llvm-svn: 31099
2006-10-21 05:52:40 +00:00
d881660366
Simplify code, no functionality change
...
llvm-svn: 31097
2006-10-21 05:42:09 +00:00
6fca75ec05
allow insertion of a conditional branch with fall-through
...
llvm-svn: 31095
2006-10-21 05:34:23 +00:00
20e75d4635
update assert message
...
llvm-svn: 31093
2006-10-21 04:42:29 +00:00
8366b874a9
bugfix
...
llvm-svn: 31074
2006-10-20 20:44:34 +00:00
c0fb567e23
Implement branch analysis/xform hooks required by the branch folding pass.
...
llvm-svn: 31065
2006-10-20 17:42:20 +00:00
0408e5b7ce
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
...
llvm-svn: 31024
2006-10-17 22:41:45 +00:00
63007919dc
remove some dead code
...
llvm-svn: 30938
2006-10-13 20:40:42 +00:00
d9e4bf5285
update comments
...
llvm-svn: 30663
2006-09-28 23:33:12 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
66ed41cac1
Can't commute shufps. The high / low parts elements come from different vectors.
...
llvm-svn: 29275
2006-07-25 20:25:40 +00:00
c0f90bef47
Commute shufps / shufpd.
...
llvm-svn: 28577
2006-05-30 23:34:30 +00:00
f21045a5cd
Somehow I lost a condition when I was shuffling some code around. Anyway,
...
only transform a shufps to pshufd when the first two operands are the same.
llvm-svn: 28575
2006-05-30 22:13:36 +00:00
c8c172eaae
Fix a build breaker.
...
llvm-svn: 28574
2006-05-30 21:45:53 +00:00
a4fc5b8699
Oops. PSHUFD is only available with SSE2.
...
llvm-svn: 28573
2006-05-30 21:30:59 +00:00
66f849bd7b
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.
...
llvm-svn: 28565
2006-05-30 20:26:50 +00:00
feca91a516
These can be transformed into lea as well. Not that we use this feature
...
currently...
llvm-svn: 28393
2006-05-19 18:43:41 +00:00
dd7230c9e0
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 28223
2006-05-11 07:33:49 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
bfc2c68386
Teach the codegen about instructions used for SSE spill code, allowing it
...
to optimize cases where it has to spill a lot
llvm-svn: 27801
2006-04-18 16:44:51 +00:00
ebf1006d16
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
e7ee6a5e32
Support for scalar to vector with zero extension.
...
llvm-svn: 27091
2006-03-24 23:15:12 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
5123346708
fix operand numbers
...
llvm-svn: 25915
2006-02-02 20:38:12 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
b3ea2677a4
Tell codegen MOVAPSrr and MOVAPDrr are copies.
...
llvm-svn: 25889
2006-02-01 23:03:16 +00:00
9d7008b08d
Properly split f32 and f64 into separate register classes for scalar sse fp
...
fixing a bunch of nasty hackery
llvm-svn: 23735
2005-10-14 22:06:00 +00:00
8293d0e232
Teach the register allocator that movaps is also a move instruction
...
llvm-svn: 22451
2005-07-16 02:00:20 +00:00
8a0933608a
First round of support for doing scalar FP using the SSE2 ISA extension and
...
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
llvm-svn: 22340
2005-07-06 18:59:04 +00:00
c88330ad13
* Remove trailing whitespace
...
* Convert tabs to spaces
llvm-svn: 21426
2005-04-21 23:38:14 +00:00
25be208e02
When commuting these instructions, make sure to actually swap the operands too.
...
llvm-svn: 19694
2005-01-19 16:55:52 +00:00
d54845f530
Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
...
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
2947801735
Teach the code generator that shrd/shld is commutable if it has an immediate.
...
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 07:11:01 +00:00
733aac1270
Disable 2->3 address promotion of add and inc instructions to LEA's. In
...
addition to being three address, LEA's don't set the flags.
This fixes 186.crafty.
llvm-svn: 19251
2005-01-02 04:18:17 +00:00
b7782d77c1
Implement the convertToThreeAddress method, add support for inverting JP/JNP
...
branches.
llvm-svn: 19247
2005-01-02 02:37:07 +00:00
4d7af1c680
Fix a warning
...
llvm-svn: 15409
2004-08-01 19:31:30 +00:00
bb635a27a4
Align breaks.
...
llvm-svn: 15371
2004-07-31 10:05:44 +00:00
fcef7655fa
Add breaks
...
llvm-svn: 15365
2004-07-31 09:53:31 +00:00
ce15f8f4c9
Simplify code a bit.
...
llvm-svn: 15364
2004-07-31 09:44:32 +00:00
aaf642103a
Correctly spell 'unconditional'.
...
llvm-svn: 15363
2004-07-31 09:41:44 +00:00
f57d78a87d
Implement insertGoto and reverseBranchCondition for the X86.
...
llvm-svn: 15362
2004-07-31 09:38:47 +00:00
ea81b79a97
A big X86 instruction rename. The instructions are renamed to make
...
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
llvm-svn: 11995
2004-02-29 08:50:03 +00:00
ed01da8f0b
Adjust to change in TII ctor arguments
...
llvm-svn: 11987
2004-02-29 06:31:44 +00:00
ca89812db7
These two virtual methods are never called.
...
llvm-svn: 11984
2004-02-29 05:59:33 +00:00
8358cc573d
Move MOTy::UseType enum into MachineOperand. This eliminates the
...
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).
llvm-svn: 11715
2004-02-22 19:23:26 +00:00
8cdd0215bf
Remove getAllocatedRegNum(). Use getReg() instead.
...
llvm-svn: 11393
2004-02-13 21:01:20 +00:00
92252f42c3
Don't use MachineOperator::is(Phys|Virt)Register
...
llvm-svn: 11276
2004-02-10 20:31:28 +00:00
259e98ed27
Tighten up checks
...
llvm-svn: 11274
2004-02-10 20:25:13 +00:00
aeb8a80c71
FpMOV is also a move instruction.
...
llvm-svn: 11055
2004-02-01 08:22:16 +00:00
52564b2071
Add TargetInstrInfo::isMoveInstr() to support coalescing in register
...
allocation.
llvm-svn: 10633
2003-12-28 17:35:08 +00:00
960707c335
Put all LLVM code into the llvm namespace, as per bug 109.
...
llvm-svn: 9903
2003-11-11 22:41:34 +00:00
482202a601
Added LLVM project notice to the top of every C++ source file.
...
Header files will be on the way.
llvm-svn: 9298
2003-10-20 19:43:21 +00:00
05e2f385a7
* Start using tablegen'd instruction descriptions
...
* Fix bug in the createNOP method, which was not marking the operands of the
generated XCHG as useanddef. I don't think this method is actually used,
so it wasn't breaking anything, but it should be fixed anyway...
llvm-svn: 7539
2003-08-03 21:55:55 +00:00
e2402c65d0
Reword to remove reference to how things worked in the past.
...
llvm-svn: 6323
2003-05-24 01:08:43 +00:00
d21a02ad58
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.
...
llvm-svn: 6320
2003-05-24 00:09:50 +00:00
b4d58d7f9e
Rename MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5272
2003-01-14 22:00:31 +00:00
b54343a64f
Add comments, switch uses/defs to match InstrInfo.def file
...
llvm-svn: 5102
2002-12-18 01:05:54 +00:00
0d80874f6c
* Move information about Implicit Defs/Uses into X86InstrInfo.def.
...
* Expose information about implicit defs/uses of register through the
MachineInstrInfo.h file.
llvm-svn: 4877
2002-12-03 05:42:53 +00:00
1a72c637fb
Added -*- C++ -*- mode to the comments.
...
llvm-svn: 4826
2002-11-22 22:42:50 +00:00
cf72e52df3
Expose base opcode
...
llvm-svn: 4742
2002-11-18 06:56:24 +00:00
0018e8d5fc
Start to add more information to instr.def
...
llvm-svn: 4741
2002-11-18 05:37:11 +00:00
9289d7d693
Reorganize printing interface a bit
...
llvm-svn: 4728
2002-11-17 22:53:13 +00:00
87b84a6913
Set the destination register field based on the target specific flags
...
llvm-svn: 4442
2002-10-30 01:15:31 +00:00
27d247978b
Rename X86InstructionInfo to X86InstrInfo
...
llvm-svn: 4413
2002-10-29 21:05:24 +00:00
f57420ee17
Minor renaming
...
llvm-svn: 4410
2002-10-29 20:48:56 +00:00
16cbd41c21
Implement MachineInstrInfo interface
...
llvm-svn: 4394
2002-10-29 17:43:19 +00:00
d92fb0058b
Initial checkin of X86 backend.
...
We can instruction select exactly one instruction 'ret void'. Wow.
llvm-svn: 4284
2002-10-25 22:55:53 +00:00
Evan Cheng