f0ed16eae5
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
...
Differential Revision: https://reviews.llvm.org/D22667
llvm-svn: 279429
2016-08-22 12:17:59 +00:00
846bdb746d
[mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions
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Differential Revision: https://reviews.llvm.org/D22347
llvm-svn: 277719
2016-08-04 11:22:52 +00:00
cba9f80ba8
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
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Differential Revision: http://reviews.llvm.org/D18824
llvm-svn: 275050
2016-07-11 07:41:56 +00:00
d2ed9c6c2c
[mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions
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Differential Revision: http://reviews.llvm.org/D16719
llvm-svn: 272764
2016-06-15 07:46:24 +00:00
4807f829b4
[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions
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Differential Revision: http://reviews.llvm.org/D19857
llvm-svn: 268491
2016-05-04 12:02:12 +00:00
b43d4bcbd5
[mips][microMIPS] Revert commit r266977
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Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...
llvm-svn: 267418
2016-04-25 15:34:57 +00:00
d370f440e2
[mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32
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Differential Revision: http://reviews.llvm.org/D19150
llvm-svn: 266977
2016-04-21 11:01:51 +00:00
3ef4dd7bc8
[mips][microMIPS] Implement LLE and SCE instructions
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Differential Revision: http://reviews.llvm.org/D11630
llvm-svn: 250379
2015-10-15 08:11:50 +00:00
a766eff5a0
[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
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Differential Revision: http://reviews.llvm.org/D11631
llvm-svn: 250377
2015-10-15 07:23:06 +00:00
bb65d730bf
[mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are tested.
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llvm-svn: 249386
2015-10-06 10:08:14 +00:00
d245267be0
[mips][disassembler] Merged disassembler tests into the corresponding ISA/ASE subdirectories.
...
llvm-svn: 249384
2015-10-06 10:02:35 +00:00
df19a5e605
[mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.
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Summary:
Some values of 'reglist' are reserved and cause the disassembler to read past
the end of the Regs array. Treat lwm32's containing reserved values as invalid
instructions.
Reviewers: zoran.jovanovic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12959
llvm-svn: 247990
2015-09-18 14:20:54 +00:00
Hrvoje Varga