45ef10f110
AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.
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Differential Revision: http://reviews.llvm.org/D17564
llvm-svn: 261862
2016-02-25 13:30:17 +00:00
7c10252943
[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.
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llvm-svn: 225432
2015-01-08 07:41:30 +00:00
4467f33e3c
Fixing Intel format of the vshufpd instruction.
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Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
llvm-svn: 191481
2013-09-27 01:44:23 +00:00
1885417372
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
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-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.
Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.
llvm-svn: 189201
2013-08-25 22:23:38 +00:00
efd67d4612
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
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Patch by Richard Mitton.
llvm-svn: 187476
2013-07-31 02:47:52 +00:00
394bf1482b
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
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llvm-svn: 179223
2013-04-10 21:52:25 +00:00
01deb5f2df
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
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llvm-svn: 160420
2012-07-18 04:11:12 +00:00
def81b9155
Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.
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The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use.
llvm-svn: 154809
2012-04-16 11:32:10 +00:00
74c282b5ef
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
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ret instructions.
llvm-svn: 154468
2012-04-11 01:10:53 +00:00
ebb10df441
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
llvm-svn: 152487
2012-03-10 07:37:27 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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llvm-svn: 140974
2011-10-02 21:08:12 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
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llvm-svn: 140370
2011-09-23 06:57:25 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
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llvm-svn: 140299
2011-09-22 07:01:50 +00:00
e812f9eed5
Add disassembler test for Intel syntax. Tests r139353.
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llvm-svn: 139356
2011-09-09 06:35:44 +00:00
Igor Breger