97d5cc165a
Making TableGen'd instruction selection code non-recursive. This fixes PR805.
...
llvm-svn: 29548
2006-08-07 22:17:58 +00:00
b359a7a69c
Remove some extraneous newlines.
...
llvm-svn: 29492
2006-08-03 00:42:26 +00:00
6379c96c07
Really add support for compilers without noinline
...
llvm-svn: 29491
2006-08-03 00:26:13 +00:00
70c4ae4bda
Pass N by reference to select functions to prevent gcc from allocating more stack.
...
llvm-svn: 29423
2006-08-01 01:07:48 +00:00
c1163d2fa7
Remove an unneeded match condition: the type check for root node has been
...
moved to outside the actual select routine.
llvm-svn: 29415
2006-07-31 19:01:58 +00:00
149130ad6b
Split each select function for a particular opcode into multiple ones. One
...
per possible ValueType of the node. e.g. Select_add is split into Select_add_i8,
Select_add_i16, etc.
For opcodes which do not produce a non-chain result, it is split on the
ValueType of its first non-chain operand. e.g. Select_store.
On X86 / Mac OS X, Select_store used to be the largest function. It had a stack
frame size of 8.5k. Now the largest one is Store_i32 with a frame size of 3.1k.
llvm-svn: 29404
2006-07-28 22:51:01 +00:00
75a22216f7
Clean up.
...
llvm-svn: 29378
2006-07-28 01:19:22 +00:00
e2a3f7014d
Rename IsFoldableBy to CanBeFoldedleBy
...
llvm-svn: 29376
2006-07-28 01:03:48 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
7b0ed57543
Remove dead code.
...
llvm-svn: 29359
2006-07-27 19:59:34 +00:00
061aba35c1
Let each target specific isel provide routine to check if a chain producing node is foldable by another.
...
llvm-svn: 29335
2006-07-27 06:36:49 +00:00
9384400d83
Fix for bug 840. Only use noinline attribute if gcc version >= 3.4
...
llvm-svn: 29311
2006-07-26 23:06:27 +00:00
774d8fd1ef
Removed a hack intended to allow (store (op (load))) folding. Will handle this with preprocessing.
...
llvm-svn: 29258
2006-07-21 22:19:51 +00:00
4b49c23571
Eliminate data relocations by using NULL instead of global empty list.
...
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
c62c697955
Also checks for noResults field.
...
llvm-svn: 29235
2006-07-20 23:36:20 +00:00
2884b5cc93
Make sub- and super- register classes const.
...
llvm-svn: 29200
2006-07-19 05:58:18 +00:00
3650465273
Fix a bug handling instructions, like blr, which just consist of a text
...
string. The return value of printInstruction should be true for these.
llvm-svn: 29196
2006-07-19 01:39:06 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
...
llvm-svn: 29193
2006-07-19 00:24:41 +00:00
aeccc6e676
Make sub- super- reg-class tables static.
...
llvm-svn: 29190
2006-07-18 22:18:31 +00:00
68ee5cfe10
Fix case where identical cases were not detected across case #0 , because
...
instructions not handled would have a case value of #0 , throwing things off.
This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter
by 25 lines.
llvm-svn: 29187
2006-07-18 19:27:30 +00:00
6e17208dff
Fix an accidentally duplicated line that caused tblgen to crash on itanium.
...
Add an assert that catches the real problem earlier.
llvm-svn: 29185
2006-07-18 19:06:01 +00:00
edee52570c
Maximally group commands. When all instructions within a command set have a
...
series of identical commands, handle them all with one switch. In the case
of the x86 at&t asm printer, only 3 switches are needed for all instructions.
llvm-svn: 29184
2006-07-18 18:28:27 +00:00
cb0c848d34
Change generator to remove operands as it processes them. No change in
...
generated file.
llvm-svn: 29183
2006-07-18 17:56:07 +00:00
9d250696b7
Handle the last operand more intelligently. When emitting the \n, also
...
return from the asmprinter to make the generated asmprinter both more
efficient and smaller.
llvm-svn: 29182
2006-07-18 17:50:22 +00:00
75dcf6cbd8
Emit switches with 1/2 cases as unconditional code or an if/then/else for
...
tidyness.
llvm-svn: 29181
2006-07-18 17:43:54 +00:00
66e288bec3
Steal bits from the asm string index to use for operand information. On both
...
x86 and ppc, this gets us 4 more bits to play with, since the string indices
both only use 12 bits.
llvm-svn: 29180
2006-07-18 17:38:46 +00:00
1ac0eb7f8b
Merge operand info and asmstr idx into a single 32-bit field. No other change.
...
llvm-svn: 29179
2006-07-18 17:32:27 +00:00
692374c748
Completely change the structure of the generated asmprinter to be more table
...
based and less switch-statements-with-hundreds-of-cases based. This shrinks
the x86 asmprinters to about 1/3 their previous size.
Other improvements coming.
llvm-svn: 29177
2006-07-18 17:18:03 +00:00
95454e7a2f
Use __attribute__((noinline)) only if compiled by gcc.
...
llvm-svn: 29161
2006-07-16 06:14:37 +00:00
87b2fe9474
Parameterize target node ValueType to allow more sharing of emit functions.
...
Also reduce the number of arguments passed to emit functions and removed a
hack.
llvm-svn: 29160
2006-07-16 06:12:52 +00:00
69367fedd2
Reduce instruction selection code size and stack frame size by factoring
...
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.
llvm-svn: 29158
2006-07-15 08:45:20 +00:00
45fcadc9f0
The generated index array should be const.
...
llvm-svn: 29155
2006-07-14 23:14:02 +00:00
e32982cc52
Emit the string information for the asm writer as a single large string
...
and index into it, instead of emitting it like this:
static const char * const OpStrs[] = {
"PHINODE\n", // PHI
0, // INLINEASM
"adc ", // ADC32mi
"adc ", // ADC32mi8
...
The old way required thousands of relocations that slows down link time and
dynamic load times.
This also cuts about 10K off each of the X86 asmprinters, and should shrink
the others as well.
llvm-svn: 29152
2006-07-14 22:59:11 +00:00
10d4b040ac
Clean up.
...
llvm-svn: 29137
2006-07-13 22:17:08 +00:00
a44f6269bf
1. Simplfy bit operations.
...
2. Coalesce instruction cases.
llvm-svn: 29135
2006-07-13 21:02:53 +00:00
23bd480cea
Move base value of instruction to lookup table to prepare for case reduction.
...
llvm-svn: 29122
2006-07-12 19:15:43 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
57e4363171
Reduce bloat in target libraries by removing per machine instruction assertion
...
from code emitter generation.
llvm-svn: 29097
2006-07-11 01:25:59 +00:00
f0858cb910
tblgen uses EH
...
llvm-svn: 29034
2006-07-07 00:21:17 +00:00
d19938834b
Ugly hack! Add helper functions InsertInFlightSetEntry and
...
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
llvm-svn: 28987
2006-06-29 23:57:05 +00:00
3c71a13e06
Fix an error message regression. Print:
...
LI8: (LI8:i64 (imm:i64):$imm)
instead of:
LI8: (LI8:MVT::i64 (imm:MVT::i64):$imm)
llvm-svn: 28868
2006-06-20 00:56:37 +00:00
c23e641055
Don't require src/dst patterns to be able to fully resolve their types,
...
because information about one can help refine the other. This allows us to
write:
def : Pat<(i32 (extload xaddr:$src, i8)),
(LBZX xaddr:$src)>;
as:
def : Pat<(extload xaddr:$src, i8),
(LBZX xaddr:$src)>;
because tblgen knows LBZX returns i32.
llvm-svn: 28865
2006-06-20 00:31:27 +00:00
9500b343db
Make sure to use the result of the pattern to infer the result type of the
...
instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>
and fixes a ppc64 issue.
llvm-svn: 28863
2006-06-20 00:18:02 +00:00
4b464768d1
Improve a comment.
...
llvm-svn: 28833
2006-06-16 18:25:06 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
5d038cf802
Allow more use of iPTR in patterns.
...
llvm-svn: 28790
2006-06-15 00:16:37 +00:00
ff7c28dfdd
Added support for variable_ops.
...
llvm-svn: 28788
2006-06-14 22:22:20 +00:00
1ce02e4c49
Fix support for optional input flag.
...
llvm-svn: 28784
2006-06-14 19:27:50 +00:00
632ee8de55
getOperandNum(): error if specified operand number is out of range.
...
llvm-svn: 28775
2006-06-13 21:47:27 +00:00
deafba0325
Wrap to 80 cols
...
llvm-svn: 28743
2006-06-09 23:59:44 +00:00
5cb722f320
Don't build tblgen with -pedantic or -Wno-long-long
...
llvm-svn: 28638
2006-06-01 18:20:23 +00:00
cc8c0233b6
Can't trust NodeDepth when checking for possibility of load folding creating
...
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.
llvm-svn: 28476
2006-05-25 20:16:55 +00:00
07a4e5ceb1
Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set"
...
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).
llvm-svn: 28458
2006-05-25 00:21:44 +00:00
e7549961cf
Don't make zero-sized static arrays
...
llvm-svn: 28448
2006-05-24 17:31:02 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
886e8f35aa
Now that iPTR is a fully resolved type. We end up losing the type check for
...
patterns that look like this:
def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.
llvm-svn: 28389
2006-05-19 07:24:32 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
...
llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
...
llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
...
represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
...
register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
21c7c23d7e
Noop instruction
...
llvm-svn: 28241
2006-05-12 07:47:00 +00:00
e2c1aedc23
Unused instruction
...
llvm-svn: 28240
2006-05-12 07:42:01 +00:00
229a6d0026
Also add super- register classes info.
...
llvm-svn: 28221
2006-05-11 07:30:26 +00:00
32982836b6
Watch out for the following case:
...
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.
llvm-svn: 28209
2006-05-10 02:47:57 +00:00
d2b8067748
Fix a load folding bug. It is exposed by a multi- resulting instructions
...
def : Pat<> pattern.
llvm-svn: 28208
2006-05-10 00:05:46 +00:00
5e7ba0b049
Add sub-register class information.
...
llvm-svn: 28195
2006-05-09 06:34:26 +00:00
386fb9b0fd
Set isStore of instructions with ISD::TRUNCSTORE root node.
...
llvm-svn: 28075
2006-05-03 02:08:34 +00:00
4b177f089e
Put instruction names into the first non TargetInstrInfo namespace found.
...
llvm-svn: 28043
2006-05-01 23:46:16 +00:00
017b93dd7c
instructions can be in different namespaces. Make sure to use the right
...
one for each instruction.
llvm-svn: 28038
2006-05-01 17:01:17 +00:00
8e63393bc3
Formating
...
llvm-svn: 28036
2006-05-01 09:30:17 +00:00
c2ef5e34a8
Mark instructions whose pattern is (store ...) isStore.
...
llvm-svn: 28032
2006-05-01 09:04:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
54acf6eddc
When isel'ing a node, mark its operands "InFlight" before selecting them. These
...
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.
llvm-svn: 28002
2006-04-28 02:08:10 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
778509c844
Don't fill in fields that no longer exist.
...
llvm-svn: 27898
2006-04-20 18:32:22 +00:00
9235d848b7
Rename AddedCost to AddedComplexity.
...
llvm-svn: 27841
2006-04-19 20:36:09 +00:00
aa3325e925
Allow "let AddedCost = n in" to increase pattern complexity.
...
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
56fdf9ed40
Add missing things to the distribution.
...
llvm-svn: 27650
2006-04-13 06:27:20 +00:00
989b16e488
Fix a typo: Instr* -> Intr*
...
llvm-svn: 27568
2006-04-10 22:02:59 +00:00
726df0bb82
Infer element types for shuffle masks
...
llvm-svn: 27456
2006-04-06 20:36:51 +00:00
09575a9b0a
rename a method, to avoid confusion with llvm intrinsics.
...
llvm-svn: 27455
2006-04-06 20:19:52 +00:00
89df307b61
Adjust the Intrinsics.gen interface a little bit
...
llvm-svn: 27345
2006-04-02 03:35:30 +00:00
470d0181e9
regenerate
...
llvm-svn: 27313
2006-03-31 21:54:11 +00:00
51ffbf18f0
Generalize the previous binary operator support and add a string concatenation
...
operation. This implements Regression/TableGen/strconcat.td.
llvm-svn: 27312
2006-03-31 21:53:49 +00:00
6b7ccbe4d8
Allow bits init values to be used in patterns, turn them into ints.
...
llvm-svn: 27286
2006-03-31 05:25:56 +00:00
03dfc41ba2
Final bugfix for PR724. GCC won't inline varargs functions, so use one to
...
validate the prototype of intrinsic functions. This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.
llvm-svn: 27283
2006-03-31 04:48:26 +00:00
3abe174165
When emitting code for the verifier, instead of emitting each case statement
...
independently, batch up checks so that identically typed intrinsics share
verifier code. This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.
llvm-svn: 27281
2006-03-31 04:24:58 +00:00
bab91842ba
regenerate
...
llvm-svn: 27264
2006-03-30 22:51:12 +00:00
b59cf3cff4
Implement Regression/TableGen/DagDefSubst.ll
...
llvm-svn: 27263
2006-03-30 22:50:40 +00:00
c2c8b58cf6
Don't sort the names before outputing the intrinsic name table. It causes a
...
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)
llvm-svn: 27237
2006-03-28 22:25:56 +00:00
7c9740a9ed
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
Also, don't emit dynamic checks when we can compute them statically
llvm-svn: 27202
2006-03-28 00:41:33 +00:00
8a2ae8b766
Only compute intrinsic valuetypes when in a target .td file.
...
llvm-svn: 27197
2006-03-28 00:15:00 +00:00
ac2512a261
revert this, it breaks things.
...
llvm-svn: 27196
2006-03-28 00:03:08 +00:00
c92f688ef3
Add support for decoding iPTR to the right pointer type.
...
llvm-svn: 27188
2006-03-27 22:48:18 +00:00
5386598187
Print error messages like this:
...
tblgen: In STVEBX: Intrinsic 'llvm.ppc.altivec.stvebx' expects 3 operands, not 2 operands!
instead of like this:
tblgen: In STVEBX: Intrinsic 'intrinsic_void expects 3 operands, not 2 operands!
llvm-svn: 27185
2006-03-27 22:21:18 +00:00
8c46ff2d12
Add a missing check which cause an invalid .td file to crash tblgen
...
llvm-svn: 27126
2006-03-25 22:12:44 +00:00
23555e3947
When failing selection for an intrinsic, print this:
...
Cannot yet select: intrinsic %llvm.ppc.altivec.lvx
instead of this:
Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540
llvm-svn: 27110
2006-03-25 06:47:53 +00:00
c8565ed651
Change approach so that we get codegen for free for intrinsics. With this,
...
intrinsics that don't take pointer arguments now work. For example, we can
compile this:
int test3( __m128d *A) {
return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
return _mm_movemask_ps(*A);
}
to this:
_test3:
movl 4(%esp), %eax
movapd (%eax), %xmm0
movmskpd %xmm0, %eax
ret
_test4:
movl 4(%esp), %eax
movaps (%eax), %xmm0
movmskps %xmm0, %eax
ret
llvm-svn: 27090
2006-03-24 23:10:39 +00:00
85586baee7
fix 80 column violations
...
llvm-svn: 27084
2006-03-24 21:52:20 +00:00
e352e7aa85
Parse intrinsics correctly and perform type propagation. This doesn't currently
...
emit the code to select intrinsics, but that is next :)
llvm-svn: 27082
2006-03-24 21:48:51 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
bbba823706
Make sure to initialize the TheDef field!
...
llvm-svn: 27078
2006-03-24 20:25:01 +00:00
2c58141fd9
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
...
the CodeGen* implementations.
Parse the MVT::ValueType for each operand of the intrinsics.
llvm-svn: 27075
2006-03-24 19:49:31 +00:00
97b0d99651
extract some more information from the intrinsic table
...
llvm-svn: 27022
2006-03-24 01:13:55 +00:00
1e0552f838
Add new generated files to be ignored.
...
llvm-svn: 27011
2006-03-23 23:45:32 +00:00
eb0ce0c547
Allow result node to be a simple leaf node. This enable bitconvert patterns
...
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
llvm-svn: 26968
2006-03-23 02:35:32 +00:00
c0af9c6478
Don't forget to promote xform function to an explicit node for def : Pat<>
...
patterns.
llvm-svn: 26929
2006-03-21 20:44:17 +00:00
02ad00ad93
minor code simplification
...
llvm-svn: 26918
2006-03-21 06:42:58 +00:00
af7de1fba8
The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
...
one, i.e. don't select it.
llvm-svn: 26909
2006-03-20 22:53:06 +00:00
5ece6fa3e0
It should be ok for a xform output type to be different from input type.
...
llvm-svn: 26899
2006-03-20 08:09:17 +00:00
a84bdebfd2
Copy matching pattern's output type info to instruction result pattern.
...
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.
llvm-svn: 26892
2006-03-20 06:04:09 +00:00
c1b31d8a83
Add a new SDTCisIntVectorOfSameSize type constraint
...
llvm-svn: 26890
2006-03-20 05:39:48 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
...
llvm-svn: 26869
2006-03-19 07:57:34 +00:00
f878f6aa54
Fix miscodegen of V_SET0 in PPC.
...
llvm-svn: 26836
2006-03-18 00:40:36 +00:00
09ffafcf54
allow the GCCBuiltinName field to be optional
...
llvm-svn: 26784
2006-03-15 19:15:26 +00:00
c4e2468251
Fix VC++ build error.
...
llvm-svn: 26773
2006-03-15 02:51:05 +00:00
1c32e04b5f
remove typo
...
llvm-svn: 26772
2006-03-15 02:05:38 +00:00
da1a4cc6a4
Autogenerate a table of intrinsic names, so we can map from intrinsic ID to
...
LLVM intrinsic function name.
llvm-svn: 26771
2006-03-15 01:55:21 +00:00
402a573764
Autogenerate code to map from GCC builtin to LLVM intrinsic.
...
llvm-svn: 26770
2006-03-15 01:33:26 +00:00
3eb12e9a2a
Add a newline at the end to avoid gcc warnings.
...
llvm-svn: 26749
2006-03-14 05:59:52 +00:00
fea17a9901
emit a mapping from LLVM intrinsic -> GCC builtins.
...
llvm-svn: 26736
2006-03-13 23:08:44 +00:00
5b6ec4a5ea
Verify that packed type operands have the right size and base type.
...
llvm-svn: 26735
2006-03-13 22:38:57 +00:00
69035f00e3
fix pasto in generate assertion msg
...
llvm-svn: 26706
2006-03-11 00:20:47 +00:00
e3c2db3955
generate side-effect info
...
llvm-svn: 26672
2006-03-09 22:37:52 +00:00
06c7300bf1
Parse mod/ref properties, autogen mod/ref information
...
llvm-svn: 26669
2006-03-09 22:30:49 +00:00
6efe863a70
parse intrinsic types
...
autogenerate an intrinsic verifier
llvm-svn: 26666
2006-03-09 22:05:04 +00:00
6d8104efd2
autogenerate the function name recognizer
...
llvm-svn: 26663
2006-03-09 20:34:19 +00:00
c47620b5d8
Temporary hack to enable more (store (op (load ...))) folding. This makes
...
it possible when a TokenFactor is between the load and store. But is still
missing some cases due to ordering issue.
llvm-svn: 26638
2006-03-09 08:19:11 +00:00
0fab08eae3
Don't generate silly matching code like this:
...
if (N1.getOpcode() == ISD::ADD &&
...)
if (... &&
(N1.getNumOperands() == 1 || !isNonImmUse(N1.Val, N10.Val))) &&
...)
TableGen knows N1 must have more than one operand.
llvm-svn: 26592
2006-03-07 08:31:27 +00:00
ae0f1512c9
Silence a warning.
...
llvm-svn: 26508
2006-03-03 19:34:28 +00:00
f6e846eee8
Fix pasteo
...
llvm-svn: 26499
2006-03-03 06:13:41 +00:00
94f300d15c
remove a bunch of long-dead testing code
...
llvm-svn: 26497
2006-03-03 02:34:28 +00:00
c313d0b712
initial implementation of intrinsic parsing
...
llvm-svn: 26495
2006-03-03 02:32:46 +00:00
73fbe145fd
remove out of date comment
...
llvm-svn: 26492
2006-03-03 02:04:07 +00:00
1edf15e48e
Add support for "-Ifoo" in addition to "-I foo"
...
llvm-svn: 26487
2006-03-03 01:53:40 +00:00
d7f6b55afa
Regenerate
...
llvm-svn: 26486
2006-03-03 01:47:37 +00:00
e7b74c5da1
add support for multiple include directories
...
llvm-svn: 26485
2006-03-03 01:47:14 +00:00
53a2d60bca
New vector type v2f32.
...
llvm-svn: 26437
2006-03-01 01:10:52 +00:00
dc445eadc0
Select inline asm memory operands.
...
llvm-svn: 26349
2006-02-24 02:13:31 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
33f4156663
Bump up pattern cost if the resulting instruction is marked
...
usesCustomDAGSchedInserter.
llvm-svn: 26282
2006-02-18 02:33:09 +00:00
3e15eac81b
Check the new form for bison output into CVS
...
llvm-svn: 26208
2006-02-15 07:24:01 +00:00
ecd162d5cd
Adjust to new form of handling lexer dependencies, this way shouldn't have
...
the problems the old way did.
llvm-svn: 26161
2006-02-14 05:13:13 +00:00
5940bc210e
Call InsertISelMapEntry rather than map insertion operator to prevent overly
...
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.
llvm-svn: 26095
2006-02-09 22:12:27 +00:00
9ce762d51f
Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
...
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
1630c2848f
Hoist all SDOperand declarations within a Select_{opcode}() to the top level
...
to reduce stack memory usage. This is intended to work around the gcc bug.
llvm-svn: 26026
2006-02-07 00:37:41 +00:00
5c76b499aa
Add support for modifier strings in machine instr descriptions. This allows
...
us to avoid creating lots of "Operand" types with different printers, instead
we can fold several together and use modifiers. For example, we can now use:
${target:call} to say that the operand should be printed like a 'call' operand.
llvm-svn: 26024
2006-02-06 23:40:48 +00:00
033e32e5d9
Simplify the variant handling code, no functionality change.
...
llvm-svn: 26023
2006-02-06 22:43:28 +00:00
ebf05bea1b
At the end of isel, select a replacement node for each handle that does not
...
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).
llvm-svn: 26014
2006-02-06 08:12:55 +00:00
308d0090e6
Name change.
...
llvm-svn: 26013
2006-02-06 06:03:35 +00:00
aa26555b25
Handle HANDLENODE: just return itself.
...
llvm-svn: 26011
2006-02-05 08:46:14 +00:00
368f20e53d
Allow more loads to be folded which were previously prevented from happening
...
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.
llvm-svn: 25995
2006-02-05 06:43:12 +00:00
7ab4579c68
Re-committing the last bit of change. It shouldn't break PPC this time.
...
llvm-svn: 25982
2006-02-05 05:22:18 +00:00
586b06281c
Temporarily revert the last change, which breaks PPC and other targets that
...
DO select things.
llvm-svn: 25970
2006-02-04 09:23:06 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
2bcfc52af6
node predicates add to the complexity of a pattern. This ensures that the
...
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.
llvm-svn: 25937
2006-02-03 18:06:02 +00:00
717db484a5
(store (op (load ...))) folding problem. In the generated matching code,
...
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.
However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.
The solution is for each chain operand to get a unique name. e.g. Chain10.
llvm-svn: 25931
2006-02-03 06:22:41 +00:00
244e800c19
add a note, ya knoe
...
llvm-svn: 25880
2006-02-01 19:12:23 +00:00
88e616d803
If a pattern's root node is a constant, its size should be 3 rather than 2.
...
llvm-svn: 25870
2006-02-01 06:06:31 +00:00
0d3ef40656
implement test/Regression/TableGen/DagIntSubst.ll
...
llvm-svn: 25836
2006-01-31 06:02:35 +00:00
a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
4d5a93ed28
Use printInlineAsm to, well, print inline asm's.
...
llvm-svn: 25677
2006-01-27 02:10:50 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
db2a5f09f1
If we want to emit things in enum order, use getInstructionsByEnumValue to
...
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
llvm-svn: 25672
2006-01-27 01:44:09 +00:00
ac8b13b32b
There is at least a 'noitinerary' itinerary now
...
llvm-svn: 25671
2006-01-27 01:41:55 +00:00
ec249a3d30
Don't emit JIT code for these instructions
...
llvm-svn: 25669
2006-01-27 01:39:38 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
dce31c8d70
fix a broken comment
...
llvm-svn: 25411
2006-01-17 21:31:18 +00:00
5ed803256d
Regenerated the Lex and Yacc output files on Linux. It seems that our
...
Linux machines don't like the source code generated on MacOS X for some
reason.
llvm-svn: 25394
2006-01-17 17:01:34 +00:00
61864ec3fe
Emit a type matching check for ComplexPatterns.
...
llvm-svn: 25392
2006-01-17 07:36:41 +00:00
a039d439dc
Type inferencing bug
...
llvm-svn: 25337
2006-01-15 10:04:45 +00:00
bd1de84121
Allow transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25252
2006-01-12 19:35:54 +00:00
e6300aaabc
GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol
...
llvm-svn: 25245
2006-01-12 07:54:57 +00:00
31686087cd
Some minor fixes.
...
llvm-svn: 25227
2006-01-11 22:16:13 +00:00
e18ad392d3
Always select target registers to themselves
...
llvm-svn: 25218
2006-01-11 19:52:27 +00:00
3857f6d067
Emit an error instead of an assertion if trying to do bogus things in result patterns.
...
llvm-svn: 25194
2006-01-11 01:33:49 +00:00
230044839d
Added support for the extractelement operation.
...
llvm-svn: 25181
2006-01-10 19:05:34 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
...
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
482ef91d26
Pattern complexity calculation fix.
...
llvm-svn: 25133
2006-01-06 22:19:44 +00:00
46634d21e3
Tweak pattern complexity calc.
...
llvm-svn: 25122
2006-01-06 02:30:23 +00:00
6b037909ff
Bug fix wrt chain operand.
...
llvm-svn: 25115
2006-01-06 00:41:12 +00:00
a69bb989f1
Replace fix with one less disruptive to the original code.
...
Also note that GCC 4.1 also correctly flags the syntax error.
llvm-svn: 25076
2006-01-04 03:23:30 +00:00
7d17a6bc86
Tblgen was generating syntactically illegal C++ code like:
...
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;
GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.
llvm-svn: 25075
2006-01-04 03:15:19 +00:00
3d38031bef
Remove obsolete comment, make things look a bit nicer
...
llvm-svn: 25070
2006-01-04 00:32:01 +00:00
c29793a077
reduce stack usage of the recursive SelectCode function by out-lining each
...
case of the switch statement into its own method.
llvm-svn: 25069
2006-01-04 00:25:00 +00:00
81e4dbc6a1
Remove my previous ugly hack that tries to reduce the stack space usage
...
of SelectCode to make way for a better solution.
llvm-svn: 25068
2006-01-03 22:55:16 +00:00
def44bec82
HP-UX DVDs are crunchy and good to eat
...
llvm-svn: 25052
2005-12-30 16:41:48 +00:00
018da4f5ef
almost got the HP-UX tester up.. :)
...
llvm-svn: 25051
2005-12-30 14:56:37 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
ccb1aebcd3
This gets most of the backends building with HP HappyC++.
...
llvm-svn: 25029
2005-12-27 10:56:22 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
14492afc23
more standards-compliance stuff
...
llvm-svn: 25014
2005-12-26 05:08:55 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
...
support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
d834d495b2
silence some bogus gcc warnings
...
llvm-svn: 24962
2005-12-22 20:37:36 +00:00
a87d743912
Attempt to fix a crash on WIN32.
...
llvm-svn: 24936
2005-12-22 02:35:21 +00:00
991bc6d6ba
* Added support for FLAG - a special nameless flag register. Can be used as
...
either an operand or a result.
* Fixed some more flag / chain bugs.
llvm-svn: 24933
2005-12-22 02:24:50 +00:00
f646926ecf
Allows instructions which no explicit operands. e.g. X86 RET which has but
...
an implicit flag operand.
llvm-svn: 24916
2005-12-21 20:20:49 +00:00
812a56e888
Eliminate some GCC warnings from the generated code
...
llvm-svn: 24897
2005-12-21 05:31:05 +00:00
4bf64a8ba4
Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail;
...
llvm-svn: 24883
2005-12-20 20:08:01 +00:00
777bb6eb45
This ugly patch works around a GCC bug where it is compiling SelectCode to
...
use too much stack space, overflowing the stack for large functions. Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.
This reduces the stack size of SelectCode from 28K to 21K. Note that GCC
compiles it to 512 bytes :-/
I've filed GCC PR 25505 to track this.
llvm-svn: 24882
2005-12-20 19:41:03 +00:00
9696f63d3e
Now support instructions with implicit write to non-flag registers.
...
llvm-svn: 24878
2005-12-20 07:37:41 +00:00
fe90b604a4
Lefted out a fix in the previous check in.
...
llvm-svn: 24873
2005-12-20 00:06:17 +00:00
19b9f15377
Fix another bug related to chain / flag.
...
llvm-svn: 24868
2005-12-19 22:40:04 +00:00
9bd85c2f19
Fixes for a number of bugs: save flag results in CodeGenMap, folded chains
...
may not all have ResNo == 0.
llvm-svn: 24858
2005-12-19 07:18:51 +00:00
f7ae0a95fe
Handle basic block nodes
...
llvm-svn: 24833
2005-12-18 21:05:44 +00:00
abb11cc83e
More fixes for Selection of copyto/fromreg with a flag
...
llvm-svn: 24829
2005-12-18 15:45:51 +00:00
fc3d4f8fd8
Select copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24827
2005-12-18 15:28:25 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
3717b4c830
Add some methods
...
llvm-svn: 24596
2005-12-05 02:35:08 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
...
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
...
llvm-svn: 24556
2005-12-01 00:12:04 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
...
ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
e479ccb27b
fit into 80 columns
...
llvm-svn: 24554
2005-11-30 23:58:18 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
...
permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
f621b333f3
Fix some copy and paste typos.
...
llvm-svn: 24540
2005-11-30 18:37:14 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
...
llvm-svn: 24519
2005-11-29 18:44:58 +00:00
4d0251ad55
Add the new vector types to tablegen
...
llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
...
to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
...
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
a70c7dff2e
Validate that the input to 'Pat' patterns is sane.
...
llvm-svn: 24393
2005-11-17 17:43:52 +00:00
2a230e1c1a
teach tblgen to be smart enough to handle tglobaladdr nodes
...
llvm-svn: 24391
2005-11-17 07:39:45 +00:00
b22950df6c
fix a tblgen bug that Evan ran into, where we would lose the '$src' name
...
on patterns like "(set R32:$dst, (i32 imm:$src))"
llvm-svn: 24383
2005-11-16 23:14:54 +00:00
d6d3afb05e
1. Remove ranges from itinerary data.
...
2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
64209fd14b
Reject integer literals that are out of range for their type.
...
llvm-svn: 24162
2005-11-03 05:46:11 +00:00
590176be16
Add support for immediates directly in the pattern, this allows itanium to
...
define:
def : Pat<(i1 1), (CMPEQ r0, r0)>;
llvm-svn: 24149
2005-11-02 06:49:14 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
9e1784d738
Keep VC++ happy.
...
llvm-svn: 24137
2005-11-01 18:04:06 +00:00
0433df136f
Emit itinerary class in instruction info.
...
llvm-svn: 24122
2005-10-31 17:16:46 +00:00
3763a50d82
Generate cpu to itinerary map.
...
llvm-svn: 24121
2005-10-31 17:16:01 +00:00
d91df9d941
Make negative immediates in patterns work correctly, silence some warnings
...
building the itanium backend.
llvm-svn: 24095
2005-10-29 16:39:40 +00:00
742606ad30
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
...
llvm-svn: 24074
2005-10-28 22:59:53 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
...
reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
802bd8d94f
Use the new interface Jim added
...
llvm-svn: 24071
2005-10-28 22:43:25 +00:00
dffe5978a3
Removed Mr. Smith from the code.
...
llvm-svn: 24070
2005-10-28 21:47:29 +00:00
b04feb633f
Added method to return a vector of records for a ListInit of Def field. This
...
simplifies using list of records.
llvm-svn: 24069
2005-10-28 21:46:31 +00:00
1959575208
Add some commentary.
...
llvm-svn: 24055
2005-10-28 15:20:43 +00:00
b0aa47b043
Keep Visual Studio happy.
...
llvm-svn: 24052
2005-10-28 01:43:09 +00:00
86f002cc32
Now generating instruction itineraries for scheduling. Not my best work, but...
...
llvm-svn: 24050
2005-10-27 19:47:21 +00:00
777a26efc3
Simplify.
...
llvm-svn: 24015
2005-10-26 17:49:21 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
f277ac7caa
Condcodes are in the ISD namespace
...
llvm-svn: 24010
2005-10-26 17:02:02 +00:00
611b0c634c
Add support for CondCode's
...
llvm-svn: 24008
2005-10-26 16:59:37 +00:00
d980c46f52
Emit some boilerplate for targets
...
llvm-svn: 23983
2005-10-25 20:35:14 +00:00
1b7369b1ae
Refactored to make room for more stuff (scheduling info.)
...
llvm-svn: 23975
2005-10-25 15:16:36 +00:00
fc9f5773d0
Fix an incompatibility with GCC 4.1, thanks to Vladimir Merzliakov
...
for pointing this out!
llvm-svn: 23963
2005-10-24 15:04:15 +00:00
4f48e67c6c
Add the needed #include, emit enums with the sizes of tables, remove
...
definitions from the LLVM namespace, since they are all static.
llvm-svn: 23907
2005-10-23 22:33:08 +00:00
49f7b69997
Remove the obsolete instr selector emitter
...
llvm-svn: 23894
2005-10-23 05:47:52 +00:00
a1beea6c7d
Sort the features and processor lists for the sake of search (and maintainers.)
...
llvm-svn: 23879
2005-10-22 07:59:56 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
cfda85ad91
New TableGen backends for subtarget information. Only command line stuff
...
active now. Scheduling itinerary next.
llvm-svn: 23869
2005-10-21 19:00:04 +00:00
8bda5afd91
Make tblgen emit:
...
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.
llvm-svn: 23854
2005-10-21 01:19:59 +00:00
c9ad735e78
add support for literal immediates in patterns to match, allowing us to
...
write things like this:
def : Pat<(add GPRC:$in, 12),
(ADD12 GPRC:$in)>;
Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819
2005-10-19 04:41:05 +00:00
7f6f565846
Add basic support for integer constants in pattern results.
...
llvm-svn: 23817
2005-10-19 04:30:56 +00:00
2ae2f99326
Fix some checking that was causing duraid to get a perplexing assertion
...
instead of a happy error message
llvm-svn: 23816
2005-10-19 04:12:14 +00:00
b8014e10ae
Add support for patterns that have physical registers in them. Testcase:
...
def : Pat<(trunc G8RC:$in),
(OR8To4 G8RC:$in, X0)>;
Even though this doesn't make any sense on PPC :)
llvm-svn: 23815
2005-10-19 02:07:26 +00:00
c8f899f98d
Asserting here is to violent
...
llvm-svn: 23814
2005-10-19 01:55:23 +00:00
8baf5043a8
Nate wants to define 'Pat's which turn into instructions that don't have
...
patterns. Certainly a logical request.
llvm-svn: 23810
2005-10-19 01:27:22 +00:00
ed653cbe43
Duraid pointed out that it is impolite to emit PPC:: into the IA64 backend
...
llvm-svn: 23780
2005-10-18 04:41:01 +00:00
825298b060
Make the generated code significantly more memory efficient, by using
...
SelectNodeTo instead of getTargetNode when possible.
llvm-svn: 23758
2005-10-16 01:41:58 +00:00
6b22d2554a
Implement the last major missing piece in the DAG isel generator: when emitting
...
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction. This allows FMA32
patterns to not match double expressions for example.
llvm-svn: 23748
2005-10-15 21:34:21 +00:00
c4db8f4163
Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
...
type constraint. This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.
llvm-svn: 23730
2005-10-14 06:25:00 +00:00
ecaf56b21a
Fairly serious rework of the typing code to add new int/fp lattice values.
...
Overall, no functionality change yet though.
llvm-svn: 23729
2005-10-14 06:12:03 +00:00
cdf483556f
simplify the code a bit
...
llvm-svn: 23728
2005-10-14 05:08:37 +00:00
4892df38f3
Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint
...
llvm-svn: 23725
2005-10-14 04:53:53 +00:00
7b0275ba8c
Implement a couple of new (important) features.
...
1. If an operation has to be int or fp and the target only supports one
int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
for patterns involving those operators, since we do not emit the code to
check for them yet. This prevents PPC from generating FP ops currently.
Also move some code around into more logical places.
llvm-svn: 23724
2005-10-14 04:11:13 +00:00
90c5b9c83c
Do not let getLegalValueTypes return a list with duplicates in it
...
llvm-svn: 23723
2005-10-14 03:54:49 +00:00
d4ff3c1324
Emit the value type for each register class.
...
llvm-svn: 23584
2005-10-02 06:23:37 +00:00
c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
...
llvm-svn: 23564
2005-09-30 17:49:27 +00:00
3e020bb619
remove some more initializers
...
llvm-svn: 23562
2005-09-30 17:41:05 +00:00
ddc69bbbba
trim down the target info structs now that we have a preferred spill register class for each callee save register
...
llvm-svn: 23560
2005-09-30 17:35:22 +00:00
da6fcc9f49
Compute a preferred spill register class for each callee-save register
...
llvm-svn: 23553
2005-09-30 06:44:45 +00:00
26f5fb1277
Fix a warning
...
llvm-svn: 23550
2005-09-30 06:09:50 +00:00
1916ef75cf
Regenerate
...
llvm-svn: 23549
2005-09-30 04:53:25 +00:00
b509577605
Refactor this a bit to move ParsingTemplateArgs to only apply to classes,
...
not defs.
Implement support for forward definitions of classes. This implements
TableGen/ForwardRef.td.
llvm-svn: 23548
2005-09-30 04:53:04 +00:00
20b0e3cee4
Regenerate
...
llvm-svn: 23546
2005-09-30 04:42:56 +00:00
ad61925e27
Generate a parse error instead of a checked exception if template args are
...
used on a def.
llvm-svn: 23545
2005-09-30 04:42:31 +00:00
6e60c8fe05
regenerate
...
llvm-svn: 23543
2005-09-30 04:11:27 +00:00
e04e1384fc
Refactor the grammar a bit to implement TableGen/ForwardRef.td
...
llvm-svn: 23542
2005-09-30 04:10:49 +00:00
2a6fd61dfc
allow regs to be in multiple reg classes
...
llvm-svn: 23540
2005-09-30 01:33:48 +00:00
366fe04301
Teach tablegen to reassociate operators when possible. This allows it to
...
find all of teh pattern matches for EQV from one definition
llvm-svn: 23529
2005-09-29 22:36:54 +00:00
e86824e57a
Teach tblgen to build permutations of instructions, so that the target author
...
doesn't have to specify them manually. It currently handles associativity,
e.g. knowing that (X*Y)+Z also matches X+(Y*Z) and will be extended in
the future.
It is smart enough to not introduce duplicate patterns or patterns that can
never match.
llvm-svn: 23526
2005-09-29 19:28:10 +00:00
492e70f4ec
add support for an associative marker
...
llvm-svn: 23502
2005-09-28 20:58:06 +00:00
8bb25cd68a
Emit an error if instructions or patterns are defined but can never match.
...
Currently we check that immediate values live on the RHS of commutative
operators. Defining ORI like this, for example:
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"ori $dst, $src1, $src2",
[(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>;
results in:
tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators!
llvm-svn: 23501
2005-09-28 19:27:25 +00:00
f74c30c281
collect commutativity information
...
llvm-svn: 23499
2005-09-28 18:28:29 +00:00
3622f15491
Prefer cheaper patterns to more expensive ones. Print the costs to the generated
...
file
llvm-svn: 23492
2005-09-28 17:57:56 +00:00
75b4c5d868
Select Constant nodes to TargetConstant nodes
...
llvm-svn: 23488
2005-09-28 16:58:06 +00:00
d455c36c91
memoize the assert results
...
llvm-svn: 23457
2005-09-26 22:10:24 +00:00
c9153266c6
Emit the switch stmt cases in alphabetical order instead of pointer order,
...
which is not stable.
llvm-svn: 23456
2005-09-26 21:59:35 +00:00
d5de8544f8
implement a fixme: only select values once, even if used multiple times.
...
llvm-svn: 23454
2005-09-26 21:53:26 +00:00
23b1d28e69
Fix VC++ build errors.
...
llvm-svn: 23431
2005-09-25 19:04:43 +00:00
cc1d38160d
memoize translations
...
llvm-svn: 23419
2005-09-24 00:50:51 +00:00
0afb14cade
Teach the DAG isel generator to emit code that creates nodes.
...
Fix a few corner cases parsing things like (i32 imm:$foo)
llvm-svn: 23417
2005-09-24 00:40:24 +00:00
cd093e868e
Emit better code (no more copies for var references), and support DAG patterns
...
(e.g. things like rotates).
llvm-svn: 23416
2005-09-23 23:16:51 +00:00
8ffb99b4fe
Fix a fixme by passing around SDOperand's instead of SDNode*'s
...
llvm-svn: 23415
2005-09-23 21:53:45 +00:00
cc8a564cb1
Emit code that matches the incoming DAG pattern and checks predicates.
...
This does not check that types match yet, but PPC only has one integer type
;-).
This also doesn't have the code to build the resultant dag.
llvm-svn: 23414
2005-09-23 21:33:23 +00:00
323a47970e
emit information about the order patterns are to be matched.
...
llvm-svn: 23413
2005-09-23 20:52:47 +00:00
abb430bad2
start filling in the switch stmt
...
llvm-svn: 23412
2005-09-23 19:36:15 +00:00
7884fffb00
Fix a minor bug, add comments
...
llvm-svn: 23370
2005-09-16 00:29:46 +00:00
59e96143a2
teach the type inference code how to infer types for instructions and node
...
xforms. Run type inference on result patterns, so we always have fully typed
results (and to catch errors in .td files).
llvm-svn: 23369
2005-09-15 22:23:50 +00:00
fedd9a5e1d
put instructions into a map instead of a vector for quick lookup
...
llvm-svn: 23368
2005-09-15 21:57:35 +00:00
f38ce8f756
when parsing instructions remember information about the types taken and
...
returned.
llvm-svn: 23367
2005-09-15 21:51:12 +00:00
a0a986c9ae
Start parsing "Pattern" nodes
...
llvm-svn: 23365
2005-09-15 21:42:00 +00:00
f79ad4cb32
rename a couple of methods, add structure for pattern parsing
...
llvm-svn: 23364
2005-09-15 02:38:02 +00:00
a155256a71
Verify that xform functions only occur in logical places
...
llvm-svn: 23363
2005-09-14 23:05:13 +00:00
991c7c973a
Promote xform fns to be explicit nodes in result patterns, and clean off
...
predicates since they will have already matched at this point.
llvm-svn: 23362
2005-09-14 23:01:59 +00:00
bc7aabce12
start building the instruction dest pattern correctly. Change the xform
...
functions to preserve the Record for the xform instead of making it into a
function name.
llvm-svn: 23361
2005-09-14 22:55:26 +00:00
e389c6154e
catch unnamed inputs
...
llvm-svn: 23360
2005-09-14 22:06:36 +00:00
030f876cf2
check that there are no unexpected operands
...
llvm-svn: 23359
2005-09-14 21:59:34 +00:00
3ced3f8b82
force all instruction operands to be named.
...
llvm-svn: 23358
2005-09-14 21:13:50 +00:00
f02994d782
Check that operands have unique names. REJECT instructions with broken operand
...
lists: only don't parse them if they are entirely missing (sparcv9).
llvm-svn: 23355
2005-09-14 21:05:02 +00:00
24ae3494f0
fix a broke range check
...
llvm-svn: 23354
2005-09-14 21:04:12 +00:00
3ba60bf644
Parse significantly more of the instruction pattern, now collecting and
...
verifying information about the operands.
llvm-svn: 23353
2005-09-14 20:53:42 +00:00
22e60c99ce
Verify that set destinations occur first in the instruction operand list.
...
llvm-svn: 23351
2005-09-14 18:19:25 +00:00
fcffc98b05
add an accessor
...
llvm-svn: 23349
2005-09-14 18:02:53 +00:00
1c8d6ce015
remove some code that isn't ready for prime time
...
llvm-svn: 23346
2005-09-14 06:03:10 +00:00
3361eab530
Switch to a slightly more structured representation for instructions
...
llvm-svn: 23345
2005-09-14 04:03:16 +00:00
4cfcb544bf
Add some more checking/verification code
...
llvm-svn: 23344
2005-09-14 02:11:12 +00:00
4c7b604091
start parsing instructions into patterns, start doing many more checks of
...
'set's.
llvm-svn: 23343
2005-09-14 00:09:24 +00:00
bb9b01644e
don't emit the namespace inside the class!
...
llvm-svn: 23341
2005-09-13 22:05:02 +00:00
70a7234111
Emit code suitable for emission into the ISel class, allowing us to use/define
...
methods.
llvm-svn: 23340
2005-09-13 22:03:37 +00:00
3556d849da
continue xform function parsing
...
llvm-svn: 23338
2005-09-13 21:59:15 +00:00
2617de498d
Start parsing node transformation information
...
llvm-svn: 23337
2005-09-13 21:51:00 +00:00
ae939eb6bb
Add a new Record::getValueAsCode method to mirror the other getValueAs*
...
methods. Use it to simplify some code.
llvm-svn: 23336
2005-09-13 21:44:28 +00:00
f365e25a5c
completely eliminate TreePattern::PatternType
...
llvm-svn: 23335
2005-09-13 21:20:49 +00:00
d0c7a5eeb7
Regenerate
...
llvm-svn: 23311
2005-09-12 05:30:06 +00:00
564d240799
Rearrange two rules, which apparently makes some versions of bison happier.
...
llvm-svn: 23310
2005-09-12 05:29:43 +00:00
0dce12dd90
Fix miscellaneous Visual Studio build problems.
...
llvm-svn: 23307
2005-09-10 02:00:02 +00:00
ce2173d098
add an accessor to provide more checking
...
llvm-svn: 23289
2005-09-09 01:15:01 +00:00
7a82c06f34
use new accessors to simplify code. Add checking to make sure top-level instr
...
definitions are void
llvm-svn: 23288
2005-09-09 01:11:44 +00:00
91d8672be1
add some accessors
...
llvm-svn: 23287
2005-09-09 01:11:17 +00:00
debd6e95ab
Fix incorrect comment
...
llvm-svn: 23285
2005-09-08 23:26:30 +00:00
d7d31f3b06
Implement a complete type inference system for dag patterns, based on the
...
constraints defined in the DAG node definitions in the .td files. This
allows us to infer (and check!) the types for all nodes in the current
ppc .td file. For example, instead of:
Inst pattern EQV: (set GPRC:i32:$rT, (xor (xor GPRC:i32:$rA, GPRC:i32:$rB), (imm)<<Predicate_immAllOnes>>))
we now fully infer:
Inst pattern EQV: (set:void GPRC:i32:$rT, (xor:i32 (xor:i32 GPRC:i32:$rA, GPRC:i32:$rB), (imm:i32)<<Predicate_immAllOnes>>))
from: (set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))
llvm-svn: 23284
2005-09-08 23:22:48 +00:00
cee994b464
Compute the value types that are natively supported by a target.
...
llvm-svn: 23282
2005-09-08 21:43:21 +00:00
1c33104010
Parse information about type constraints on SDNodes
...
llvm-svn: 23281
2005-09-08 21:27:15 +00:00
a3b89dfcef
use node info in the one place we currently use it
...
llvm-svn: 23280
2005-09-08 21:04:46 +00:00
35bcd1488a
start parsing SDNode info records
...
llvm-svn: 23279
2005-09-08 21:03:01 +00:00
07f1e4597e
Fix indentation
...
llvm-svn: 23276
2005-09-08 19:47:28 +00:00
bd6b164965
regenerate
...
llvm-svn: 23275
2005-09-08 18:48:47 +00:00
972cccd77a
Add support for automatically created anonymous definitions.
...
This implements Regression/TableGen/AnonDefinitionOnDemand.td
llvm-svn: 23274
2005-09-08 18:48:23 +00:00
5a699e621f
regenerate
...
llvm-svn: 23271
2005-09-08 18:22:57 +00:00
8a41b214b3
Tabs to spaces.
...
llvm-svn: 23270
2005-09-08 18:22:35 +00:00
399f59f643
Keep names even when inlining. This allows us to realize that ADDI is:
...
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>:$imm))
not:
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>))
(we keep the ":$imm")
llvm-svn: 23269
2005-09-08 17:45:12 +00:00
d2a5b366f5
Initial cut of the dag isel generator. This is still very much a work in
...
progress. It correctly parses instructions and pattern fragments and glues
together pattern fragments into instructions.
The only code it generates currently is some boilerplate code for things
like the EntryNode.
llvm-svn: 23261
2005-09-07 23:44:43 +00:00
c59a1dbce2
Rename a class. These files are being migrated to the new isel and I want to
...
reuse the names
llvm-svn: 23252
2005-09-06 22:51:34 +00:00
784e44443d
regenerate
...
llvm-svn: 23249
2005-09-06 21:23:27 +00:00
ab9eba1014
Tighten up the specification to allow TableGen/nested-comment.td to pass
...
(fixing a bug where / in a /* */ comment would cause it to not close).
llvm-svn: 23248
2005-09-06 21:23:09 +00:00
90d000417f
Add an option and stuff implementation of a dag isel emitter
...
llvm-svn: 23236
2005-09-03 01:14:03 +00:00
dfb3fb4a25
Implement PR614:
...
These changes modify the makefiles so that the output of flex and bison are
placed in the SRC directory, not the OBJ directory. It is intended that they
be checked in as any other LLVM source so that platforms without convenient
access to flex/bison can be compiled. From now on, if you change a .y or
.l file you *must* also commit the generated .cpp and .h files.
llvm-svn: 23115
2005-08-27 18:50:39 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
63dc7f569a
spell this variable right
...
llvm-svn: 23095
2005-08-26 20:42:52 +00:00
3d9fbefbf7
Expose a new flag to TargetInstrInfo
...
llvm-svn: 23094
2005-08-26 20:40:46 +00:00
c36c9bdb5d
add a marker at the end of the instruction enum list
...
llvm-svn: 23090
2005-08-26 20:17:00 +00:00
96d0234845
Emit this:
...
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };
instead of this:
static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };
For operand information, which does not require dynamic (startup-time)
initialization.
llvm-svn: 22931
2005-08-19 20:29:14 +00:00
8ed3d0a0ce
Expose the derived register classes to the public header, allowing them
...
to be accessed.
llvm-svn: 22930
2005-08-19 20:23:42 +00:00
73ec2cb0f5
Split register class "Methods" into MethodProtos and MethodBodies
...
llvm-svn: 22928
2005-08-19 19:12:51 +00:00
74f60c306d
Refactor to use Target.getRegisterClasses consistently, which provides
...
anonymous regclass definition renaming.
Change the generated code to emit register classes as properly namespace
qualified entities like everything else.
expose the actual class definition as an object, though this isn't quite
usable yet.
llvm-svn: 22920
2005-08-19 18:47:59 +00:00
d02bd5bb05
Emit real operand info for instructions. This currently works but is bad
...
in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
llvm-svn: 22919
2005-08-19 18:46:26 +00:00
418d8cfcfe
Read the namespace field from register classes
...
llvm-svn: 22918
2005-08-19 18:45:20 +00:00
f9b2edb91f
add a setName method to record
...
llvm-svn: 22912
2005-08-19 17:58:49 +00:00
ac284259ac
Add a setName method to Record.
...
llvm-svn: 22911
2005-08-19 17:58:11 +00:00
220d00109b
For now, just emit empty operand info structures.
...
llvm-svn: 22910
2005-08-19 16:57:28 +00:00
0899614152
Fix a problem jeffc noticed
...
llvm-svn: 22903
2005-08-19 06:16:04 +00:00
04a5ae3f71
The code emitter generator only supports targets with 32-bit instruction
...
words. There is no way for one of these targets to have a > 32-bit immediate!
llvm-svn: 22897
2005-08-19 01:04:33 +00:00
511ee687e5
now that all of the targets are clean w.r.t. the number of operands for each
...
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter
llvm-svn: 22895
2005-08-19 00:59:49 +00:00
17727bad02
Figure out how many operands each instruction has, keep track of whether
...
or not it's variable.
llvm-svn: 22885
2005-08-18 23:38:41 +00:00
b015303c5e
revert this change, which causes breakage, temporarily
...
llvm-svn: 22880
2005-08-18 22:12:31 +00:00
99df668f48
When emitting implicit use/def lists, only emit each unique list once. Though
...
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
llvm-svn: 22879
2005-08-18 21:36:47 +00:00
6f52a04fc7
Fill in the numOperands field of the TargetInstrDescriptor struct from the
...
.td file.
llvm-svn: 22873
2005-08-18 19:45:37 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
3a6a4d3707
Fix PR595: These error messages should not be looking at CGI.Name, they
...
should be looking at CGI.TheDef->getName().
llvm-svn: 22445
2005-07-15 22:43:04 +00:00
4f229d5197
Add support for a TODO; instructions in .td files can now have arguments
...
printed as part of the opcode. This allows something like
cmp${cc}ss in the x86 backed to be printed as cmpltss, cmpless, etc.
depending on what the value of $cc is.
llvm-svn: 22439
2005-07-14 22:50:30 +00:00
88e7b7288a
Eliminate tabs and trailing spaces
...
llvm-svn: 21441
2005-04-22 04:13:13 +00:00
650ba8eb56
Remove trailing whitespace
...
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
14db4a2895
ignore generated files
...
llvm-svn: 21362
2005-04-19 15:34:36 +00:00
b17483028f
fix bogus warning
...
llvm-svn: 21361
2005-04-19 15:32:30 +00:00
ef94374a1c
Major change to tblgen: instead of resolving values every time a class is
...
finished up, only resolve fully when the def is defined. This allows things
to be changed and all uses to be propagated through. This implements
TableGen/LazyChange.td and fixes TemplateArgRename.td in the process.
None of the .td files used in LLVM backends are changed at all by this
patch.
llvm-svn: 21344
2005-04-19 03:36:21 +00:00
3ff0e11294
implementing shifting of literal integers
...
llvm-svn: 21336
2005-04-19 01:17:35 +00:00
101fc501d0
Add initial lexer and parser support for shifting values. Every use of this
...
will lead to it being rejected though.
llvm-svn: 21335
2005-04-19 01:11:03 +00:00
97cf8fd4a9
Minor fix.
...
llvm-svn: 19761
2005-01-22 20:59:38 +00:00
59a7f5c2f3
This is the final big of factoring. This shares cases in suboperand
...
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
llvm-svn: 19760
2005-01-22 20:31:17 +00:00
92275bb6bb
Implement *even more* factoring. In particular, if all of the instruction
...
strings starts out with a constant string, we emit the string first, using
a table lookup (instead of a switch statement).
Because this is usually the opcode portion of the asm string, the differences
between the instructions have now been greatly reduced. This allows many
more case statements to be grouped together.
This patch also allows instruction cases to be grouped together when the
instruction patterns are exactly identical (common after the opcode string
has been ripped off), and when the differing operand is a MachineInstr
operand that needs to be formatted.
The end result of this is a mean and lean generated AsmPrinter!
llvm-svn: 19759
2005-01-22 19:22:23 +00:00
945e8655dd
Refactor code for numbering instructions into CodeGenTarget.
...
llvm-svn: 19758
2005-01-22 18:58:51 +00:00
da636b3783
Fix VC++ compilation error
...
llvm-svn: 19757
2005-01-22 18:50:10 +00:00
9ceb7c8f23
Implement factoring of instruction pattern strings. In particular, instead of
...
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
llvm-svn: 19755
2005-01-22 18:38:13 +00:00
b6f5d9a82a
Fix the ::: problem
...
llvm-svn: 19754
2005-01-22 18:18:59 +00:00
3baf682110
Minor refactoring, no functionality change.
...
llvm-svn: 19753
2005-01-22 17:40:38 +00:00
0c23ba5c0f
Seperate asmstring parsing from emission. This allows the code to be simpler
...
and more understandable. It also allows us to do simple things like fold
consequtive literal strings together. For example, instead of emitting this
for the X86 backend:
O << "adc" << "l" << " ";
we now generate this:
O << "adcl ";
*whoa* :)
This shrinks the X86 asmwriters from 62729->58267 and 65176->58644 bytes
for the intel/att asm writers respectively.
llvm-svn: 19749
2005-01-22 17:32:42 +00:00
67e2e21353
make double-dollar properly escape asmstrings
...
llvm-svn: 19740
2005-01-22 00:35:22 +00:00
733c82bfbf
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
...
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
1c48c2deee
For PR387:
...
Make this compile without warning when -Woverloaded-virtual is used.
llvm-svn: 18588
2004-12-06 23:42:37 +00:00
b2d0fa0823
Fix usage of changed function prototype
...
llvm-svn: 17798
2004-11-14 22:30:54 +00:00
429aaa5855
Quiet VC++ warnings
...
llvm-svn: 17484
2004-11-05 04:50:59 +00:00
f88808ae43
Internalize variable names to prevent recursive assignment. Cleanup docs.
...
llvm-svn: 17359
2004-10-30 09:19:36 +00:00
57cbe39d1e
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
7dfc2d29ac
Convert 'struct' to 'class' in various places to adhere to the coding standards
...
and work better with VC++. Patch contributed by Morten Ofstad!
llvm-svn: 17281
2004-10-27 16:14:51 +00:00
87a1061559
Make VC happier, patch contributed by Morten Ofstad
...
llvm-svn: 17179
2004-10-23 04:58:50 +00:00
5fd95ce095
We're not doing automake any more
...
llvm-svn: 17168
2004-10-22 21:02:23 +00:00
c1c320c335
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
6a11a75f31
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
8393c15b28
* Factor out (into new fn) a loop emitting operand shifts into the instruction
...
* Reverse instruction bit components for a LittleEndian-style encoding
* Fix some comments and spacing
llvm-svn: 16975
2004-10-14 05:53:01 +00:00
243ded5e1a
* Add option to read isLittleEndianEncoding for InstrInfo classes
...
* Doxygen-ify some function comments
llvm-svn: 16974
2004-10-14 05:50:43 +00:00
ac1a547a38
Patch to make VS happier, thanks to Morten Ofstad for pointing this out.
...
llvm-svn: 16956
2004-10-13 15:25:46 +00:00
26bfe011f8
Updates for changes in Makefile rules.
...
llvm-svn: 16951
2004-10-13 11:48:50 +00:00
5499551206
Don't emit the method into the llvm namespace, let the #includer decide where it goes
...
llvm-svn: 16934
2004-10-12 16:21:18 +00:00
b84cbf2725
Initial version of automake Makefile.am file.
...
llvm-svn: 16885
2004-10-10 20:43:57 +00:00
41f9f29996
Properly `quote' names, and don't forget to add the ending quote!
...
llvm-svn: 16838
2004-10-08 14:59:05 +00:00
72770f5877
Correctly parse variant notation
...
llvm-svn: 16637
2004-10-03 20:19:02 +00:00
91c538f2a1
Add initial support for variants. This just parses the new format, no
...
functionality is added
llvm-svn: 16636
2004-10-03 19:34:31 +00:00
46cee7da73
#include DataTypes.h to compile on MinGW, patch by Henrik Bach.
...
llvm-svn: 16616
2004-09-30 18:27:39 +00:00
996ddbc98e
Add support for the isLoad and isStore flags, needed by the instruction scheduler
...
llvm-svn: 16554
2004-09-28 21:01:45 +00:00
9b0dfa3c0d
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
...
llvm-svn: 16553
2004-09-28 18:38:01 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
0ded30aec4
Clean up some "clean:" targets so they use $(VERB) and don't print anything
...
by default, like every other "clean" target in LLVM.
llvm-svn: 16161
2004-09-03 23:19:53 +00:00
c8ec13388b
Make tblgen's exception handling a little more robust by printing the
...
program name and also catching ...
llvm-svn: 16160
2004-09-03 23:17:54 +00:00
7c16caa336
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
811c3c0edb
Link with LLVMsystem.a for operating system independence.
...
llvm-svn: 16094
2004-08-29 19:31:19 +00:00
9b129bea2e
RemoveFileOnErrorSignal is now in the llvm::sys namespace. Adjust
...
accordingly.
llvm-svn: 16093
2004-08-29 19:30:41 +00:00
8eab62ee0d
Alignment is now in bits.
...
llvm-svn: 15976
2004-08-21 20:15:25 +00:00
beadefde19
Make alignment be in bits, just like size is
...
llvm-svn: 15969
2004-08-21 20:00:36 +00:00
a6d34d9e19
Infer the spillsize/alignment of a register based on the register classes
...
it is embedded into.
llvm-svn: 15966
2004-08-21 19:42:03 +00:00
d3244d9cec
Support "Methods" in register classes in CodgeGenRegisterClass
...
llvm-svn: 15965
2004-08-21 19:21:21 +00:00
2a86fab933
Start parsing register classes into a more structured form
...
llvm-svn: 15961
2004-08-21 04:05:00 +00:00
e34ae99942
Read in declared reg sizes
...
llvm-svn: 15960
2004-08-21 02:24:57 +00:00
c9d99efdd3
Do not #include files into the llvm namespace
...
llvm-svn: 15849
2004-08-17 03:08:28 +00:00
8af61ddb96
Use CodeGenRegister class to make reading in of register information more
...
systematic.
llvm-svn: 15805
2004-08-16 01:10:21 +00:00
b7b70480e1
Add initial support for register and register class representation.
...
Obviously this is not done.
llvm-svn: 15804
2004-08-16 01:09:52 +00:00
0bbf7005f5
Remove awareness of isDummyClass
...
llvm-svn: 15789
2004-08-15 23:04:13 +00:00
6ffa501d9f
Make the AsmWriter a first-class tblgen object. Allow targets to specify
...
name of the generated asmwriter class, and the name of the format string.
llvm-svn: 15747
2004-08-14 22:50:53 +00:00
baa2ecb798
Fix minor bug in previous checkin
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llvm-svn: 15649
2004-08-11 04:08:36 +00:00
c1904dd38f
change how we invoke the printer. Instead of passing in the MO directly,
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pass in the MI, operand number, and the type of the operand.
llvm-svn: 15645
2004-08-11 02:23:23 +00:00
3bc477a237
Start parsing more information from the Operand information
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llvm-svn: 15644
2004-08-11 02:22:39 +00:00
101f3fea82
Remove special case hacks
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llvm-svn: 15643
2004-08-11 01:53:58 +00:00
422d0fadf1
Deleted commented-out code as we now get namespace directly, add comments
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llvm-svn: 15627
2004-08-10 20:54:58 +00:00
59978333a3
Use the target name instead of hard-coding SparcV9.
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llvm-svn: 15616
2004-08-10 18:31:01 +00:00
79db057a3b
This was a good idea, but until this does not break the build of
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lib/Target/Sparc, we should not use it.
llvm-svn: 15603
2004-08-10 15:05:18 +00:00
920ae9524d
Use the current target name instead of a ClassPrefix.
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llvm-svn: 15585
2004-08-09 19:10:43 +00:00
18d27dc342
* Use Classname and ClassPrefix instead of hard-coded V9 values
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* Simplify code and shorten lines by not recomputing values
llvm-svn: 15582
2004-08-09 17:47:45 +00:00
8e5492e350
* Added documentation in the file header
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* Shorten assert() text to make it fit within 80 cols
llvm-svn: 15508
2004-08-04 22:07:54 +00:00
f40e4ebf19
Be picky
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llvm-svn: 15400
2004-08-01 08:55:34 +00:00
29d8ac77e1
Instructions no longer need to have names.
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llvm-svn: 15399
2004-08-01 08:38:17 +00:00
65512a0c49
Add support for asm printing machine instructions that have operands.
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llvm-svn: 15391
2004-08-01 07:43:02 +00:00
5572682faa
Parse the operand list of the instruction. We currently support register and immediate operands.
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llvm-svn: 15390
2004-08-01 07:42:39 +00:00
1c4ae85035
Initial cut at an asm writer emitter. So far, this only handles emission of
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instructions, and only instructions that take no operands at that!
llvm-svn: 15386
2004-08-01 05:59:33 +00:00
c860ecafe1
Add, and start using, the CodeGenInstruction class. This class represents
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an instance of the Instruction tablegen class.
llvm-svn: 15385
2004-08-01 05:04:00 +00:00
fce9603387
Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
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llvm-svn: 15382
2004-08-01 04:04:35 +00:00
6847866400
Finegrainify namespacification
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llvm-svn: 15381
2004-08-01 03:55:39 +00:00
fd4558862c
Support new flag
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llvm-svn: 15355
2004-07-31 02:07:26 +00:00
577fc3f576
Implement test/Regression/TableGen/ListSlices.td
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llvm-svn: 15249
2004-07-27 01:01:21 +00:00
8bf9e06ddd
Add initial support for list slices. This currently allows you to do stuff
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like this:
def B {
list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6];
}
... which isn't particularly useful, but more is to come.
llvm-svn: 15247
2004-07-26 23:21:34 +00:00
87bf918bc0
Remove some abandoned code that was never finished. If needed in the future
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it can be ressurected from CVS.
llvm-svn: 15113
2004-07-22 21:32:38 +00:00
89ae115aa5
Passing integer 0 in for a pointer value doesn't work on IA64. Fix this
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by using a new macro.
llvm-svn: 14863
2004-07-16 00:02:21 +00:00
8e30a4dfc5
Make tblgen not try to be smart. This is better handled in makefiles if
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at all. Patch contributed by Vladimir Prus!
llvm-svn: 14784
2004-07-13 06:11:46 +00:00
6752fb58b6
Handle shifts >= 32 bits.
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llvm-svn: 14291
2004-06-21 18:01:47 +00:00
bcdadf3765
Move the IntrinsicLowering header into the CodeGen directory, as per PR346
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llvm-svn: 14266
2004-06-20 07:49:54 +00:00
b8561ebf21
Make header comment fit within 80 cols.
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llvm-svn: 14198
2004-06-17 15:49:36 +00:00
aff10d0461
Emit a more sensible error message if no subclasses of Target are defined.
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Patch contributed by Vladimir Prus.
llvm-svn: 14010
2004-06-04 14:59:42 +00:00
1f4e545a89
Add support for dos style files.
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llvm-svn: 13836
2004-05-27 17:44:18 +00:00
278f5152d3
Header file moved
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llvm-svn: 13813
2004-05-27 05:41:36 +00:00
b4f20ea496
The "best" of both worlds: readable C++ comments and valid HTML For doxygen.
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llvm-svn: 12964
2004-04-15 15:30:15 +00:00
68a9025f50
Tablegen backend for really simple instruction selector
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llvm-svn: 12713
2004-04-06 19:31:31 +00:00
f9bfc7f927
add tablgen backend for really simple instruction selector
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llvm-svn: 12712
2004-04-06 19:30:56 +00:00
36326de312
Do not remove an active template argument even if the superclass had one of the
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same name
llvm-svn: 11950
2004-02-28 17:41:48 +00:00
994f2d1406
Ignore X = X assignments that was causing Alkis's rewrite of X86.td to crash
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tblgen.
llvm-svn: 11948
2004-02-28 17:31:28 +00:00
d959ab9208
Assert instead of going into an infinite loop!
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llvm-svn: 11946
2004-02-28 16:31:53 +00:00
564251ed5e
exit(1) instead of abort()'ing on error
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llvm-svn: 11380
2004-02-13 16:37:43 +00:00
a80e9f0a19
Fix buggy error message problem
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llvm-svn: 11379
2004-02-13 16:33:56 +00:00
e10e2b12dd
Ooops, top-level C++-comments aren't recognized by flex.
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llvm-svn: 11337
2004-02-12 00:03:08 +00:00
a01b30bbaa
* Convert C comments to C++ style (why are some one way, some another?!)
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* Delete extra space, extra blank comment lines
* Convert function comments to doxygen
llvm-svn: 11336
2004-02-12 00:00:46 +00:00
e6540165b3
Print the record NAME not the record ADDRESS
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llvm-svn: 11144
2004-02-06 03:19:17 +00:00
666aaf715f
Fix a couple of places I noticed where "X86" was hard-coded.
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llvm-svn: 10974
2004-01-24 09:23:46 +00:00
95c13c92ff
Stop laughing Misha
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llvm-svn: 10393
2003-12-11 00:58:34 +00:00
960707c335
Put all LLVM code into the llvm namespace, as per bug 109.
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llvm-svn: 9903
2003-11-11 22:41:34 +00:00
9583cfafc5
Added LLVM copyright notice.
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llvm-svn: 9324
2003-10-21 15:29:18 +00:00
abe5cdcf21
Added LLVM copyright to Makefiles.
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llvm-svn: 9314
2003-10-20 22:29:16 +00:00
d3032037f1
Added LLVM copyright header.
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llvm-svn: 9305
2003-10-20 20:20:30 +00:00
38a47ab007
Removed the .PRECIOUS of Lex and Yacc output files.
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They are already marked precious in llvm/Makefile.rules, and removing
this line seems to fix the Makefile so that the Yacc output is placed
into the object tree and not the source tree.
llvm-svn: 9179
2003-10-16 20:38:16 +00:00
44d2c3514a
Regularize header file comments
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llvm-svn: 9071
2003-10-13 03:32:08 +00:00
969378468e
This seems to work around some unobvious bug in gcc on sparc which was
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causing the build of lib/Target/X86 to fail.
llvm-svn: 9042
2003-10-10 21:55:29 +00:00
5f1f337d95
Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
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and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:
if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}
was changed to:
for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}
llvm-svn: 8960
2003-10-08 05:20:08 +00:00
f5bd1b7a8e
Move support/tools/* back into utils
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llvm-svn: 8875
2003-10-05 19:27:59 +00:00
Evan Cheng