8fefeffb37
Because we promote SSE logical ops and loads to v2i64, we often end up generate
...
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.
llvm-svn: 40076
2007-07-20 00:27:43 +00:00
9081ab8127
Oops. These stores actually produce results.
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llvm-svn: 40074
2007-07-20 00:20:46 +00:00
64738536b3
Fix custom lowering of SSE FXOR.
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llvm-svn: 40071
2007-07-19 23:36:01 +00:00
7ca3555bfa
Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).
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llvm-svn: 40070
2007-07-19 23:34:10 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
22b0c344db
Only adjust esp around calls in presence of alloca.
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llvm-svn: 40030
2007-07-19 00:42:58 +00:00
7b5b06805a
Only adjust esp around calls in presence of alloca.
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llvm-svn: 40028
2007-07-19 00:42:05 +00:00
8941071ae1
Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.
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llvm-svn: 40018
2007-07-18 21:26:06 +00:00
776962a97a
Implement initial memory alignment awareness for SSE instructions. Vector loads
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and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
llvm-svn: 40015
2007-07-18 20:23:34 +00:00
f314055706
New entry.
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llvm-svn: 39998
2007-07-18 08:21:49 +00:00
97b5dc63d7
Fold prologue esp update when possible.
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llvm-svn: 39984
2007-07-17 21:26:42 +00:00
b2bb4b4040
Make sure not to break eh_return.
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llvm-svn: 39978
2007-07-17 18:40:47 +00:00
27ba94bf3b
Update.
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llvm-svn: 39977
2007-07-17 18:39:45 +00:00
67e2e22e97
Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.
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llvm-svn: 39974
2007-07-17 18:03:34 +00:00
9ae2eb43d8
Use push / pop for prologues and epilogues.
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llvm-svn: 39967
2007-07-17 07:59:08 +00:00
396156e00b
no email addrs in file headers
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llvm-svn: 39962
2007-07-17 05:56:43 +00:00
06c60b6032
Fix comments about vectors to use the current wording.
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llvm-svn: 39921
2007-07-16 14:29:03 +00:00
383a324735
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
1fae1cd3e1
Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
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llvm-svn: 39843
2007-07-13 23:55:50 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
2b4d9b684f
Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551)
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llvm-svn: 39813
2007-07-13 16:24:10 +00:00
85ee72f7ba
ARM: make branch folder remove unconditional branches
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following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
llvm-svn: 39782
2007-07-12 16:45:35 +00:00
bdc69595d9
another missed SSE optimization
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llvm-svn: 39772
2007-07-12 06:31:38 +00:00
bcda5e20c9
Added support for Mips specific GAS directives
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Fixed print immediate
Fixed Identation on MipsISelDAGToDAG.cpp
llvm-svn: 39764
2007-07-11 23:24:41 +00:00
6c8c748e4d
Added support for framepointer
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Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!
llvm-svn: 39763
2007-07-11 23:21:31 +00:00
77dbdcabf2
Now that stack is represented the right way, LOA starts at 0
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llvm-svn: 39761
2007-07-11 23:17:41 +00:00
4449e5dd7f
Fixed AddLiveOut issues
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FI's created the write way to represent Mips stack
llvm-svn: 39760
2007-07-11 23:16:16 +00:00
c5affeccbd
Removed unused immediate PatLeaf, fixed lui instruction
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llvm-svn: 39759
2007-07-11 22:47:02 +00:00
753e37027f
Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog
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llvm-svn: 39758
2007-07-11 22:44:21 +00:00
3d70855dd2
Handle packed structs in the CBackend.
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llvm-svn: 39752
2007-07-11 19:56:53 +00:00
e59411d056
Fix hang compiling TimberWolf (allow for islands
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of size other than 4).
llvm-svn: 39743
2007-07-11 18:32:38 +00:00
09d73c0305
Assert when TLS is not implemented.
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llvm-svn: 39737
2007-07-11 17:19:51 +00:00
6e544a9cca
Fix an oversight: for modules with no other identifying target info,
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the sparc backend should be preferred when running on sparcs.
llvm-svn: 39142
2007-07-11 16:32:10 +00:00
94579dbd2e
Didn't mean the last commit. Revert.
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llvm-svn: 38515
2007-07-10 22:00:16 +00:00
68471d263f
Fix fp_constant_op failure.
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llvm-svn: 38514
2007-07-10 21:53:30 +00:00
effa7467b6
Update.
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llvm-svn: 38513
2007-07-10 21:49:47 +00:00
23f631d87c
fix 80 columnn violations, increasing the world's
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pedantic satisfaction level.
llvm-svn: 38512
2007-07-10 20:53:41 +00:00
f51bd666d9
add a note
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llvm-svn: 38507
2007-07-10 20:03:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
0867337075
Remove clobbersPred.
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llvm-svn: 38500
2007-07-10 18:07:08 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
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in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
881248c4e1
No need for ccop anymore.
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llvm-svn: 37965
2007-07-06 23:34:09 +00:00
3650b2c278
Incorrect check.
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llvm-svn: 37962
2007-07-06 23:23:19 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
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llvm-svn: 37960
2007-07-06 23:22:03 +00:00
b039c60889
Do away with ImmutablePredicateOperand.
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llvm-svn: 37959
2007-07-06 23:21:02 +00:00
b567e3ffb0
Add the byval attribute
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llvm-svn: 37940
2007-07-06 10:57:03 +00:00
0a42fdf346
Print the s bit if the instruction is toggled to its CPSR setting form.
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llvm-svn: 37932
2007-07-06 01:01:34 +00:00
Evan Cheng