df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
d4d255a408
Use getSectionForFunction
...
llvm-svn: 30739
2006-10-05 02:48:40 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
d61d39ec53
Adding dllimport, dllexport and external weak linkage types.
...
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
llvm-svn: 30374
2006-09-14 18:23:27 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
12e97307a1
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
0fc4541c67
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
bad9d2ee49
Use a couple of multiclass patterns to factor some integer ops.
...
llvm-svn: 30039
2006-09-01 22:28:02 +00:00
38e6d1d5af
remove a bunch of comments
...
llvm-svn: 30038
2006-09-01 22:16:22 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
ab8297f92d
Match tblgen changes.
...
llvm-svn: 29895
2006-08-26 01:07:58 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
63d178f473
SelectNodeTo() may return a SDOperand that is different from the input.
...
llvm-svn: 29726
2006-08-16 07:30:09 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
dc1614d93e
Add support for the missing FP condition codes
...
llvm-svn: 28482
2006-05-25 22:26:02 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
f7db631b7d
Sparc is big-endian.
...
llvm-svn: 28415
2006-05-20 00:49:30 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
...
This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
9cd2ef34e6
Remove dead variable.
...
llvm-svn: 28247
2006-05-12 17:31:21 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
8587f8885d
Some notes and thoughts to myself
...
llvm-svn: 28182
2006-05-09 04:58:46 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
9857229aba
Add the README files to the distribution.
...
llvm-svn: 27651
2006-04-13 06:39:24 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
bb84eae239
D'oh - should be even numbered.
...
llvm-svn: 27088
2006-03-24 22:48:02 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
...
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
...
llvm-svn: 26403
2006-02-27 20:09:23 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
...
it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
...
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
...
CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
...
intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
...
llvm-svn: 26106
2006-02-10 06:58:25 +00:00
4c0bd5bcdf
Done
...
llvm-svn: 26091
2006-02-09 20:00:19 +00:00
5259aa1c86
Enable LSR by default for SPARC: it is a clear win.
...
llvm-svn: 26090
2006-02-09 19:59:55 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
c75d5b093d
add an option to turn on LSR.
...
llvm-svn: 26080
2006-02-09 05:06:36 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
463fa70eaa
Fix the Sparc backend with Evan's recent tblgen changes
...
llvm-svn: 26009
2006-02-05 08:35:50 +00:00
a28b764886
Use SelectRoot() as the entry to any tblgen based isel.
...
llvm-svn: 25998
2006-02-05 06:51:51 +00:00
a3e5b2c61c
remove V8 reference
...
llvm-svn: 25991
2006-02-05 06:32:59 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
...
llvm-svn: 25985
2006-02-05 05:50:24 +00:00
94e95d2b3e
Great renaming: Sparc --> SparcV9
...
llvm-svn: 11826
2004-02-25 18:44:15 +00:00
10a32da382
FunctionLiveVarInfo.h moved: include/llvm/CodeGen -> lib/Target/Sparc/LiveVar
...
llvm-svn: 11804
2004-02-24 19:46:00 +00:00
8358cc573d
Move MOTy::UseType enum into MachineOperand. This eliminates the
...
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).
llvm-svn: 11715
2004-02-22 19:23:26 +00:00
76b2ff4ded
Adjustments to support the new ConstantAggregateZero class
...
llvm-svn: 11474
2004-02-15 05:55:15 +00:00
5a92240270
Use newly added next() and prior() utility functions.
...
llvm-svn: 11430
2004-02-14 01:18:34 +00:00
8cdd0215bf
Remove getAllocatedRegNum(). Use getReg() instead.
...
llvm-svn: 11393
2004-02-13 21:01:20 +00:00
cbf0667743
Squish warning
...
llvm-svn: 11375
2004-02-13 16:14:50 +00:00
c07b64f3cb
Remove this MachineOpCodeFlags assertion - its test can never be false.
...
llvm-svn: 11342
2004-02-12 04:01:07 +00:00
80da865f77
Change MachineBasicBlock's vector of MachineInstr pointers into an
...
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
llvm-svn: 11340
2004-02-12 02:27:10 +00:00
b22186adf0
MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.
...
llvm-svn: 11335
2004-02-11 20:47:34 +00:00
8f4142616d
Increase constness.
...
llvm-svn: 11322
2004-02-11 17:55:09 +00:00
2f21547208
Remove assert as the only integer registers on the sparc are physical.
...
llvm-svn: 11317
2004-02-11 06:04:51 +00:00
fcb99fe370
Fix previous broken commit. A MachineOperand may have opType ==
...
MO_VirtualRegister but if the register number is one of a physical
register is it considered as a physical register.
llvm-svn: 11315
2004-02-11 05:55:00 +00:00
adcc14d96a
Remove assert as it is meaningless. MachineOperands can be tagged as
...
MO_VirtualRegister but actually be representing a physical register.
llvm-svn: 11310
2004-02-11 04:52:30 +00:00
1cb6d2697d
Stop using this method
...
llvm-svn: 11282
2004-02-10 21:12:06 +00:00
2d5feb5e04
Remvoe use of MO.isVirtualRegister(), turn an assertion into an assert()
...
llvm-svn: 11280
2004-02-10 20:47:24 +00:00
2aea68ccfd
Remove use of isPhysicalRegister
...
llvm-svn: 11277
2004-02-10 20:35:42 +00:00
ff04d76c57
Fix PR228: [sparc] Boolean constants are emitted as true and false
...
I will observe that the concept of using WriteAsOperand is completely broken,
but then we all knew that, didn't we?
llvm-svn: 11255
2004-02-10 05:16:44 +00:00
7f7a842bd6
Doxygenify comments.
...
llvm-svn: 11252
2004-02-09 23:18:42 +00:00
4dc5478fbc
Fix PR#226: When emitting padding, always emit it as bytes. Bytes can be
...
placed into any alignment situation.
llvm-svn: 11247
2004-02-09 22:15:33 +00:00
Evan Cheng