342 lines
11 KiB
C++
342 lines
11 KiB
C++
//===-- MipsExpandPseudoInsts.cpp - Expand pseudo instructions ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, and other late
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// optimizations. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-pseudo"
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namespace {
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class MipsExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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MipsExpandPseudo() : MachineFunctionPass(ID) {}
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const MipsInstrInfo *TII;
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const MipsSubtarget *STI;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override {
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return "Mips pseudo instruction expansion pass";
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}
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private:
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bool expandAtomicCmpSwap(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAtomicCmpSwapSubword(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NMBB);
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bool expandMBB(MachineBasicBlock &MBB);
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};
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char MipsExpandPseudo::ID = 0;
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}
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static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs) {
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for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
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MBB->addLiveIn(*I);
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}
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bool MipsExpandPseudo::expandAtomicCmpSwapSubword(
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MachineBasicBlock &BB, MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI) {
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MachineFunction *MF = BB.getParent();
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const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
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DebugLoc DL = I->getDebugLoc();
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unsigned LL, SC;
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unsigned ZERO = Mips::ZERO;
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unsigned BNE = Mips::BNE;
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unsigned BEQ = Mips::BEQ;
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unsigned SEOp =
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I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_FRAG ? Mips::SEB : Mips::SEH;
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if (STI->inMicroMipsMode()) {
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LL = Mips::LL_MM;
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SC = Mips::SC_MM;
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} else {
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LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
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: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
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SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
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: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
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}
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unsigned Dest = I->getOperand(0).getReg();
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unsigned Ptr = I->getOperand(1).getReg();
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unsigned Mask = I->getOperand(2).getReg();
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unsigned ShiftCmpVal = I->getOperand(3).getReg();
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unsigned Mask2 = I->getOperand(4).getReg();
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unsigned ShiftNewVal = I->getOperand(5).getReg();
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unsigned ShiftAmnt = I->getOperand(6).getReg();
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LivePhysRegs LiveRegs(&TII->getRegisterInfo());
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for (auto MBBI = std::prev(BB.end()); MBBI != I; --MBBI)
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LiveRegs.stepBackward(*MBBI);
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB.getBasicBlock();
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MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB.getIterator();
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, sinkMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), &BB,
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std::next(MachineBasicBlock::iterator(I)), BB.end());
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exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
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// thisMBB:
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// ...
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// fallthrough --> loop1MBB
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BB.addSuccessor(loop1MBB, BranchProbability::getOne());
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loop1MBB->addSuccessor(sinkMBB);
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loop1MBB->addSuccessor(loop2MBB);
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loop2MBB->addSuccessor(loop1MBB);
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loop2MBB->addSuccessor(sinkMBB);
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sinkMBB->addSuccessor(exitMBB, BranchProbability::getOne());
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// loop1MBB:
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// ll dest, 0(ptr)
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// and Mask', dest, Mask
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// bne Mask', ShiftCmpVal, exitMBB
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BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(loop1MBB, DL, TII->get(Mips::AND), Mask)
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.addReg(Dest)
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.addReg(Mask);
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BuildMI(loop1MBB, DL, TII->get(BNE))
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.addReg(Mask).addReg(ShiftCmpVal).addMBB(sinkMBB);
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loop1MBB->addLiveIn(Ptr);
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loop1MBB->addLiveIn(Mask);
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loop1MBB->addLiveIn(ShiftCmpVal);
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// loop2MBB:
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// and dest, dest, mask2
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// or dest, dest, ShiftNewVal
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// sc dest, dest, 0(ptr)
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// beq dest, $0, loop1MBB
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BuildMI(loop2MBB, DL, TII->get(Mips::AND), Dest)
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.addReg(Dest, RegState::Kill)
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.addReg(Mask2);
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BuildMI(loop2MBB, DL, TII->get(Mips::OR), Dest)
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.addReg(Dest, RegState::Kill)
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.addReg(ShiftNewVal);
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BuildMI(loop2MBB, DL, TII->get(SC), Dest)
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.addReg(Dest, RegState::Kill)
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.addReg(Ptr)
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.addImm(0);
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BuildMI(loop2MBB, DL, TII->get(BEQ))
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.addReg(Dest, RegState::Kill)
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.addReg(ZERO)
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.addMBB(loop1MBB);
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loop2MBB->addLiveIn(Ptr);
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loop2MBB->addLiveIn(Mask2);
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loop2MBB->addLiveIn(Dest);
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loop2MBB->addLiveIn(ShiftNewVal);
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// sinkMBB:
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// srl srlres, Mask', shiftamt
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// sign_extend dest,srlres
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BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
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.addReg(Mask)
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.addReg(ShiftAmnt);
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if (STI->hasMips32r2()) {
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BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
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} else {
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const unsigned ShiftImm =
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I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I16_FRAG ? 16 : 24;
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BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
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.addReg(Dest, RegState::Kill)
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.addImm(ShiftImm);
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BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
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.addReg(Dest, RegState::Kill)
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.addImm(ShiftImm);
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}
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sinkMBB->addLiveIn(Mask);
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sinkMBB->addLiveIn(ShiftAmnt);
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addPostLoopLiveIns(exitMBB, LiveRegs);
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exitMBB->addLiveIn(Dest);
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NMBBI = BB.end();
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I->eraseFromParent();
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return true;
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}
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bool MipsExpandPseudo::expandAtomicCmpSwap(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI) {
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const unsigned Size = I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
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MachineFunction *MF = BB.getParent();
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const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
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DebugLoc DL = I->getDebugLoc();
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LivePhysRegs LiveRegs(&TII->getRegisterInfo());
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LiveRegs.addLiveOuts(BB);
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for (auto MBBI = std::prev(BB.end()); MBBI != I; --MBBI)
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LiveRegs.stepBackward(*MBBI);
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unsigned LL, SC, ZERO, BNE, BEQ;
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if (Size == 4) {
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if (STI->inMicroMipsMode()) {
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LL = Mips::LL_MM;
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SC = Mips::SC_MM;
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} else {
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LL = STI->hasMips32r6()
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? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
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: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
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SC = STI->hasMips32r6()
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? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
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: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
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}
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ZERO = Mips::ZERO;
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BNE = Mips::BNE;
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BEQ = Mips::BEQ;
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} else {
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LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
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SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
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ZERO = Mips::ZERO_64;
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BNE = Mips::BNE64;
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BEQ = Mips::BEQ64;
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}
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unsigned Dest = I->getOperand(0).getReg();
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unsigned Ptr = I->getOperand(1).getReg();
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unsigned OldVal = I->getOperand(2).getReg();
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unsigned NewVal = I->getOperand(3).getReg();
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB.getBasicBlock();
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MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB.getIterator();
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), &BB,
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std::next(MachineBasicBlock::iterator(I)), BB.end());
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exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
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// thisMBB:
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// ...
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// fallthrough --> loop1MBB
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BB.addSuccessor(loop1MBB, BranchProbability::getOne());
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loop1MBB->addSuccessor(exitMBB);
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loop1MBB->addSuccessor(loop2MBB);
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loop2MBB->addSuccessor(loop1MBB);
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loop2MBB->addSuccessor(exitMBB);
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// loop1MBB:
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// ll dest, 0(ptr)
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// bne dest, oldval, exitMBB
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BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(loop1MBB, DL, TII->get(BNE))
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.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
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loop1MBB->addLiveIn(Ptr);
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loop1MBB->addLiveIn(OldVal);
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// loop2MBB:
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// sc success, newval, 0(ptr)
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// beq success, $0, loop1MBB
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BuildMI(loop2MBB, DL, TII->get(SC), NewVal)
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.addReg(NewVal).addReg(Ptr).addImm(0);
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BuildMI(loop2MBB, DL, TII->get(BEQ))
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.addReg(NewVal, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
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loop2MBB->addLiveIn(Ptr);
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loop2MBB->addLiveIn(NewVal);
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addPostLoopLiveIns(exitMBB, LiveRegs);
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NMBBI = BB.end();
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I->eraseFromParent();
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return true;
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}
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bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NMBB) {
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bool Modified = false;
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switch (MBBI->getOpcode()) {
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case Mips::ATOMIC_CMP_SWAP_I32:
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case Mips::ATOMIC_CMP_SWAP_I64:
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return expandAtomicCmpSwap(MBB, MBBI, NMBB);
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case Mips::ATOMIC_CMP_SWAP_I8_FRAG:
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case Mips::ATOMIC_CMP_SWAP_I16_FRAG:
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return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);
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default:
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return Modified;
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}
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}
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bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool MipsExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
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TII = STI->getInstrInfo();
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bool Modified = false;
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for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
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++MFI)
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Modified |= expandMBB(*MFI);
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return Modified;
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}
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/// createMipsExpandPseudoPass - returns an instance of the pseudo instruction
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/// expansion pass.
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FunctionPass *llvm::createMipsExpandPseudoPass() {
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return new MipsExpandPseudo();
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}
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