David Sherwood 013358632e [AArch64][SME] Add the zero intrinsic ... The SME zero instruction takes a mask as an input declaring which 64-bit element tiles should be zeroed. There is a 1:1 mapping between the zero intrinsic and the instruction, however we also want to make the register allocator aware that some tile registers are being written to. We can actually just use the custom inserter for a pseudo instruction to correctly mark all the appropriate registers in the mask as implicitly defined by the operation. Differential Revision: https://reviews.llvm.org/D127843		2022-06-20 14:27:59 +01:00
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AArch64	[AArch64][SME] Add the zero intrinsic	2022-06-20 14:27:59 +01:00
AMDGPU	[AMDGPU] Increase instruction cache line size to 128 bytes for GFX11	2022-06-20 14:25:10 +01:00
ARC	…
ARM	[DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m)	2022-06-20 08:37:38 +01:00
AVR	[FileCheck] Catch missspelled directives.	2022-05-26 11:37:19 +01:00
BPF	[BPF] Add BTF 64bit enum value support	2022-06-06 11:35:50 -07:00
CSKY	…
DirectX	[DirectX] Add DirectX target object writer	2022-06-17 21:33:08 -05:00
Generic	[llvm][DWARF] Move test using X86 triple into X86 tests	2022-05-26 09:27:23 +00:00
Hexagon	[DAG] SimplifyDemandedBits - add ISD::VSELECT handling	2022-06-19 15:18:25 +01:00
Inputs	…
Lanai	[Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace	2022-05-30 19:19:23 +01:00
LoongArch	[LoongArch] Add codegen support for part of conversion operations	2022-06-20 10:00:20 +08:00
M68k	[M68k] Instruction selection to choose neg x when mul x -1 (Fix issue 48588)	2022-06-03 13:20:30 +08:00
MIR	Reland "Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI""""	2022-06-17 21:34:05 +08:00
MLRegalloc	…
MSP430	…
Mips	llvm-reduce: Don't assert on functions which don't track liveness	2022-06-07 10:00:25 -04:00
NVPTX	[NVPTX] Enable AtomicExpandPass for NVPTX	2022-05-20 17:25:28 -04:00
PowerPC	[PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and MFVSCR as not swappable.	2022-06-17 10:14:24 -05:00
RISCV	[SelectionDAG] Enable WidenVecOp_VECREDUCE_SEQ for scalable vector	2022-06-20 06:30:26 +00:00
SPARC	[SPARC] Fix type for i64 inline asm operands	2022-06-04 18:32:16 -04:00
SPIRV	[SPIRV] Add simple tests to improve test coverage	2022-05-19 01:44:38 +03:00
SystemZ	[SystemZ][z/OS] Add llvm.read_register() intrinsic support for zOS	2022-06-10 12:30:07 -04:00
Thumb	Revert "[ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records AND [NFC][Thumb] Update frame-chain codegen test to use thumbv6m"	2022-06-15 16:10:02 +02:00
Thumb2	[ARM] Allow distributing postinc with PHI uses	2022-06-20 10:08:21 +01:00
VE	…
WebAssembly	[WebAssembly][NFC] Update reftype and table tests to use opaque pointers	2022-06-20 10:57:41 +01:00
WinCFGuard	…
WinEH	…
X86	[DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m)	2022-06-20 08:37:38 +01:00
XCore	…