llvm-project/llvm/test/CodeGen
Jun Bum Lim 2ecb7ba4c6 [CodeGen] Add a new pass for PostRA sink
Summary:
This pass sinks COPY instructions into a successor block, if the COPY is not
used in the current block and the COPY is live-in to a single successor
(i.e., doesn't require the COPY to be duplicated).  This avoids executing the
the copy on paths where their results aren't needed.  This also exposes
additional opportunites for dead copy elimination and shrink wrapping.

These copies were either not handled by or are inserted after the MachineSink
pass. As an example of the former case, the MachineSink pass cannot sink
COPY instructions with allocatable source registers; for AArch64 these type
of copy instructions are frequently used to move function parameters (PhyReg)
into virtual registers in the entry block..

For the machine IR below, this pass will sink %w19 in the entry into its
successor (%bb.1) because %w19 is only live-in in %bb.1.

```
   %bb.0:
      %wzr = SUBSWri %w1, 1
      %w19 = COPY %w0
      Bcc 11, %bb.2
    %bb.1:
      Live Ins: %w19
      BL @fun
      %w0 = ADDWrr %w0, %w19
      RET %w0
    %bb.2:
      %w0 = COPY %wzr
      RET %w0
```
As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
able to see %bb.0 as a candidate.

With this change I observed 12% more shrink-wrapping candidate and 13% more dead copies deleted  in spec2000/2006/2017 on AArch64.

Reviewers: qcolombet, MatzeB, thegameg, mcrosier, gberry, hfinkel, john.brawn, twoh, RKSimon, sebpop, kparzysz

Reviewed By: sebpop

Subscribers: evandro, sebpop, sfertile, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41463

llvm-svn: 328237
2018-03-22 20:06:47 +00:00
..
AArch64 [CodeGen] Add a new pass for PostRA sink 2018-03-22 20:06:47 +00:00
AMDGPU [InstSimplify] fp_binop X, NaN --> NaN 2018-03-21 19:31:53 +00:00
ARC
ARM Run dos2unix on a test. NFC. 2018-03-20 01:06:29 +00:00
AVR [AVR] Add a regression test for struct return lowering 2018-03-20 11:23:03 +00:00
BPF bpf: Extends zero extension elimination beyond comparison instructions 2018-03-13 06:47:03 +00:00
Generic [MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default." 2018-03-19 13:37:04 +00:00
Hexagon [CodeGen] Add a new pass for PostRA sink 2018-03-22 20:06:47 +00:00
Inputs
Lanai Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
MIR [MIR] Allow frame-setup and frame-destroy on the same instruction 2018-03-13 19:53:16 +00:00
MSP430
Mips [FastISel] Sink local value materializations to first use 2018-03-14 21:54:21 +00:00
NVPTX [NVPTX] Make tensor shape part of WMMA intrinsic's name. 2018-03-21 21:55:02 +00:00
Nios2
PowerPC [POWER9][NFC] update testcase check statements 2018-03-21 20:59:45 +00:00
RISCV [RISCV] Codegen support for RV32F floating point comparison operations 2018-03-21 15:11:02 +00:00
SPARC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
SystemZ [SystemZ] Add "REQUIRES: asserts" to test case to fix build bots. 2018-03-20 08:29:19 +00:00
Thumb [ARM] Fix access to stack arguments when re-aligning SP in Armv6m 2018-03-02 15:47:14 +00:00
Thumb2 [CodeGen] Add a new pass for PostRA sink 2018-03-22 20:06:47 +00:00
WebAssembly [WebAssembly] Strip threadlocal attribute from globals in single thread mode 2018-03-20 22:01:32 +00:00
WinCFGuard
WinEH
X86 [CodeGen] Add a new pass for PostRA sink 2018-03-22 20:06:47 +00:00
XCore [XCore] Return true in enableMultipleCopyHints(). 2018-02-26 08:03:32 +00:00