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0b3661b7ce
llvm-project
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llvm
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test
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CodeGen
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MIR
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Adrian Prantl
6b44541015
Convert the CodeGen/ARM/sched-it-debug-nodes.ll testcase from IR -> MIR.
...
NFC PR24563 llvm-svn: 256187
2015-12-21 19:44:42 +00:00
..
AArch64
MIR Serialization: Use the global value syntax for global value memory operands.
2015-08-20 00:20:03 +00:00
AMDGPU
MIR Serialization: Change MIR syntax - use custom syntax for MBBs.
2015-08-13 23:10:16 +00:00
ARM
Convert the CodeGen/ARM/sched-it-debug-nodes.ll testcase from IR -> MIR.
2015-12-21 19:44:42 +00:00
Generic
MIR Serialization: Change MIR syntax - use custom syntax for MBBs.
2015-08-13 23:10:16 +00:00
Mips
[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.
2015-10-15 14:34:23 +00:00
NVPTX
MIR Serialization: Change MIR syntax - use custom syntax for MBBs.
2015-08-13 23:10:16 +00:00
PowerPC
Fix PR 24724 - The implicit register verifier shouldn't assume certain operand
2015-09-10 14:04:34 +00:00
X86
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
2015-12-01 05:29:22 +00:00
lit.local.cfg
Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).
2015-05-27 18:02:19 +00:00