122 lines
3.5 KiB
LLVM
122 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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; FUNC-LABEL: {{^}}i32_mad24:
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; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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; EG: MULLO_INT
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; Make sure we aren't masking the inputs.
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; CM-NOT: AND
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; CM: MULADD_INT24
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; GCN-NOT: and
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; GCN: v_mad_i32_i24
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define amdgpu_kernel void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = ashr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = ashr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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%3 = add i32 %2, %c
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad24_known_bits_destroyed:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mad_i32_i24
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; GCN-NEXT: v_mul_i32_i24
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; GCN-NEXT: s_setpc_b64
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define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
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%shl.0 = shl i32 %a, 8
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%sra.0 = ashr i32 %shl.0, 8
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%shl.1 = shl i32 %b, 8
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%sra.1 = ashr i32 %shl.1, 8
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%mul0 = mul nsw i32 %sra.0, %sra.1
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%add0 = add nsw i32 %mul0, %c
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%shl.2 = shl i32 %add0, 8
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%sra.2 = ashr i32 %shl.2, 8
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%shl.3 = shl i32 %sra.0, 8
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%sra.3 = ashr i32 %shl.3, 8
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%mul1 = mul nsw i32 %sra.2, %sra.3
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ret i32 %mul1
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}
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; GCN-LABEL: {{^}}mad24_intrin_known_bits_destroyed:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mad_i32_i24
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; GCN-NEXT: v_mul_i32_i24
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; GCN-NEXT: s_setpc_b64
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define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
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%shl.0 = shl i32 %a, 8
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%sra.0 = ashr i32 %shl.0, 8
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%shl.1 = shl i32 %b, 8
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%sra.1 = ashr i32 %shl.1, 8
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%mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1)
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%add0 = add nsw i32 %mul0, %c
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%shl.2 = shl i32 %add0, 8
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%sra.2 = ashr i32 %shl.2, 8
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%shl.3 = shl i32 %sra.0, 8
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%sra.3 = ashr i32 %shl.3, 8
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%mul1 = mul nsw i32 %sra.2, %sra.3
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ret i32 %mul1
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}
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; Make sure no unnecessary BFEs are emitted in the loop.
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; GCN-LABEL: {{^}}mad24_destroyed_knownbits_2:
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, i32 addrspace(1)* %arg3) {
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bb:
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br label %bb6
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bb5: ; preds = %bb6
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ret void
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bb6: ; preds = %bb6, %bb
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%tmp = phi i32 [ %tmp27, %bb6 ], [ 0, %bb ]
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%tmp7 = phi i32 [ %arg2, %bb6 ], [ 1, %bb ]
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%tmp8 = phi i32 [ %tmp26, %bb6 ], [ %arg, %bb ]
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%tmp9 = shl i32 %tmp7, 8
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%tmp10 = ashr exact i32 %tmp9, 8
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%tmp11 = shl i32 %tmp8, 8
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%tmp12 = ashr exact i32 %tmp11, 8
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%tmp13 = mul nsw i32 %tmp12, %tmp10
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%tmp14 = add nsw i32 %tmp13, %tmp7
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%tmp15 = shl i32 %tmp14, 8
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%tmp16 = ashr exact i32 %tmp15, 8
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%tmp17 = mul nsw i32 %tmp16, %tmp10
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%tmp18 = add nsw i32 %tmp17, %tmp14
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%tmp19 = shl i32 %tmp18, 8
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%tmp20 = ashr exact i32 %tmp19, 8
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%tmp21 = mul nsw i32 %tmp20, %tmp16
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%tmp22 = add nsw i32 %tmp21, %tmp18
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%tmp23 = shl i32 %tmp22, 8
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%tmp24 = ashr exact i32 %tmp23, 8
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%tmp25 = mul nsw i32 %tmp24, %tmp20
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%tmp26 = add nsw i32 %tmp25, %tmp22
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store i32 %tmp26, i32 addrspace(1)* %arg3
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%tmp27 = add nuw i32 %tmp, 1
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%tmp28 = icmp eq i32 %tmp27, %arg1
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br i1 %tmp28, label %bb5, label %bb6
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}
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declare i32 @llvm.amdgcn.mul.i24(i32, i32)
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