80 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			80 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			LLVM
		
	
	
	
| ; RUN: llc < %s -march=x86-64 -mcpu=penryn -mattr=+avx2 | FileCheck %s
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| 
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| 
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| define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) {
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| entry:
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| ; CHECK: sdiv_vec8x16
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| ; CHECK: psraw  $15
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| ; CHECK: vpsrlw  $11
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| ; CHECK: vpaddw
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| ; CHECK: vpsraw  $5
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| ; CHECK: ret
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|   %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
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|   ret <8 x i16> %0
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| }
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| 
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| define <4 x i32> @sdiv_zero(<4 x i32> %var) {
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| entry:
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| ; CHECK: sdiv_zero
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| ; CHECK-NOT: sra
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| ; CHECK: ret
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|   %0 = sdiv <4 x i32> %var, <i32 0, i32 0, i32 0, i32 0>
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|   ret <4 x i32> %0
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| }
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| 
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| define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {
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| entry:
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| ; CHECK: sdiv_vec4x32
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| ; CHECK: vpsrad $31
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| ; CHECK: vpsrld $28
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| ; CHECK: vpaddd
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| ; CHECK: vpsrad $4
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| ; CHECK: ret
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| %0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>
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| ret <4 x i32> %0
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| }
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| 
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| define <4 x i32> @sdiv_negative(<4 x i32> %var) {
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| entry:
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| ; CHECK: sdiv_negative
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| ; CHECK: vpsrad $31
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| ; CHECK: vpsrld $28
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| ; CHECK: vpaddd
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| ; CHECK: vpsrad $4
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| ; CHECK: vpsubd
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| ; CHECK: ret
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| %0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16>
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| ret <4 x i32> %0
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| }
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| 
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| define <8 x i32> @sdiv8x32(<8 x i32> %var) {
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| entry:
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| ; CHECK: sdiv8x32
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| ; CHECK: vpsrad $31
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| ; CHECK: vpsrld $26
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| ; CHECK: vpaddd
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| ; CHECK: vpsrad $6
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| ; CHECK: ret
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| %0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
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| ret <8 x i32> %0
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| }
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| 
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| define <16 x i16> @sdiv16x16(<16 x i16> %var) {
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| entry:
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| ; CHECK: sdiv16x16
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| ; CHECK: vpsraw  $15
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| ; CHECK: vpsrlw  $14
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| ; CHECK: vpaddw
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| ; CHECK: vpsraw  $2
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| ; CHECK: ret
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|   %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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|   ret <16 x i16> %a0
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| }
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| 
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| ; CHECK: sdiv_non_splat
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| ; CHECK: idivl
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| ; CHECK: ret
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| define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
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|   %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
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|   ret <4 x i32> %y
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| } |