| .. |
|
AsmParser
|
[RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer()
|
2022-08-31 11:15:47 -07:00 |
|
Disassembler
|
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
|
2022-05-15 08:44:58 +08:00 |
|
MCTargetDesc
|
[llvm] Use std::size instead of llvm::array_lengthof
|
2022-09-08 09:01:53 -06:00 |
|
TargetInfo
|
[RISCV] Re-enable JIT support
|
2022-08-11 11:41:02 +02:00 |
|
CMakeLists.txt
|
[RISCV] Add a RISCV specific CodeGenPrepare pass.
|
2022-07-14 10:20:59 -07:00 |
|
RISCV.h
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
RISCV.td
|
[RISCV][MC] Add minimal support for Ztso extension
|
2022-09-07 09:30:57 -07:00 |
|
RISCVAsmPrinter.cpp
|
[RISC-V][HWASAN] Fold variable into assert
|
2022-08-29 00:32:37 +02:00 |
|
RISCVCallLowering.cpp
|
…
|
|
|
RISCVCallLowering.h
|
…
|
|
|
RISCVCallingConv.td
|
…
|
|
|
RISCVCodeGenPrepare.cpp
|
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
|
2022-08-12 22:21:05 -07:00 |
|
RISCVExpandAtomicPseudoInsts.cpp
|
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
|
2022-08-17 13:49:15 +01:00 |
|
RISCVExpandPseudoInsts.cpp
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
RISCVFrameLowering.cpp
|
[RISCV] Handle register spill in branch relaxation
|
2022-08-24 13:27:56 +08:00 |
|
RISCVFrameLowering.h
|
[RISCV][NFCI] Set TransientStackAlignment and rely on it rather than RVV-specific logic on RVV-less functions
|
2022-08-02 09:46:06 +01:00 |
|
RISCVGatherScatterLowering.cpp
|
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
|
2022-06-10 13:00:20 -07:00 |
|
RISCVISelDAGToDAG.cpp
|
[RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy operand.
|
2022-09-13 10:09:49 +08:00 |
|
RISCVISelDAGToDAG.h
|
[RISCV] Peephole optimization to fold merge.vvm and unmasked intrinsics.
|
2022-08-11 17:58:11 +08:00 |
|
RISCVISelLowering.cpp
|
[RISCV] Custom type legalize i32 loads by sign extending.
|
2022-09-12 09:13:07 -07:00 |
|
RISCVISelLowering.h
|
[RISCV] Improve vector fceil/ffloor lowering by changing FRM.
|
2022-09-05 19:03:44 -07:00 |
|
RISCVInsertVSETVLI.cpp
|
[RISCVInsertVSETVLI] Remove an unsound optimization
|
2022-08-05 12:13:08 -07:00 |
|
RISCVInstrFormats.td
|
…
|
|
|
RISCVInstrFormatsC.td
|
…
|
|
|
RISCVInstrFormatsV.td
|
…
|
|
|
RISCVInstrInfo.cpp
|
[RISCV] : Add support for simm10_lsb0000nonzero operand.
|
2022-08-26 14:37:37 +08:00 |
|
RISCVInstrInfo.h
|
Remove redundaunt virtual specifiers (NFC)
|
2022-07-25 23:00:59 -07:00 |
|
RISCVInstrInfo.td
|
[RISCV] Improve vector fceil/ffloor lowering by changing FRM.
|
2022-09-05 19:03:44 -07:00 |
|
RISCVInstrInfoA.td
|
[RISCV] Add target feature to force-enable atomics
|
2022-08-09 16:04:46 +02:00 |
|
RISCVInstrInfoC.td
|
[RISCV] : Add support for simm10_lsb0000nonzero operand.
|
2022-08-26 14:37:37 +08:00 |
|
RISCVInstrInfoD.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVInstrInfoF.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVInstrInfoM.td
|
[RISCV][Clang] Add support for Zmmul extension
|
2022-07-18 20:26:08 -04:00 |
|
RISCVInstrInfoV.td
|
[RISCV] Add Uses=[FRM] and mayRaiseFPException to VF(N/W)CVT instructions.
|
2022-08-29 09:26:33 -07:00 |
|
RISCVInstrInfoVPseudos.td
|
[RISCV] Improve vector fceil/ffloor lowering by changing FRM.
|
2022-09-05 19:03:44 -07:00 |
|
RISCVInstrInfoVSDPatterns.td
|
[RISCV] Increase complexity of RVV element extraction patterns
|
2022-07-11 10:53:15 +08:00 |
|
RISCVInstrInfoVVLPatterns.td
|
[RISCV] Improve vector fceil/ffloor lowering by changing FRM.
|
2022-09-05 19:03:44 -07:00 |
|
RISCVInstrInfoZb.td
|
[RISCV] : Add support for immediate operands.
|
2022-08-24 17:48:39 +08:00 |
|
RISCVInstrInfoZfh.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVInstrInfoZicbo.td
|
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
|
2022-09-01 13:49:55 +01:00 |
|
RISCVInstrInfoZk.td
|
…
|
|
|
RISCVInstructionSelector.cpp
|
…
|
|
|
RISCVLegalizerInfo.cpp
|
…
|
|
|
RISCVLegalizerInfo.h
|
…
|
|
|
RISCVMCInstLower.cpp
|
[RISCV] Pre-RA expand pseudos pass
|
2022-07-31 23:19:00 +02:00 |
|
RISCVMachineFunctionInfo.cpp
|
llvm-reduce: Add cloning of target MachineFunctionInfo
|
2022-06-07 10:14:48 -04:00 |
|
RISCVMachineFunctionInfo.h
|
[RISCV] Handle register spill in branch relaxation
|
2022-08-24 13:27:56 +08:00 |
|
RISCVMacroFusion.cpp
|
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
|
2022-08-21 10:58:15 -07:00 |
|
RISCVMacroFusion.h
|
[RISCV] Add macrofusion infrastructure and one example usage.
|
2022-06-23 08:38:39 -07:00 |
|
RISCVMakeCompressible.cpp
|
[RISCV] Fix wrong register rename for store value during make-compressible optimization
|
2022-07-08 18:07:17 +08:00 |
|
RISCVMergeBaseOffset.cpp
|
[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
|
2022-08-02 15:27:23 -07:00 |
|
RISCVRedundantCopyElimination.cpp
|
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
|
2022-08-29 09:05:53 -07:00 |
|
RISCVRegisterBankInfo.cpp
|
…
|
|
|
RISCVRegisterBankInfo.h
|
…
|
|
|
RISCVRegisterBanks.td
|
…
|
|
|
RISCVRegisterInfo.cpp
|
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
|
2022-08-24 14:16:20 +00:00 |
|
RISCVRegisterInfo.h
|
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
|
2022-08-24 14:16:20 +00:00 |
|
RISCVRegisterInfo.td
|
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
|
2022-08-24 14:16:20 +00:00 |
|
RISCVSExtWRemoval.cpp
|
[Target] Qualify auto in range-based for loops (NFC)
|
2022-08-28 17:35:09 -07:00 |
|
RISCVSchedRocket.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVSchedSiFive7.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVSchedule.td
|
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
|
2022-09-12 09:37:28 -07:00 |
|
RISCVScheduleB.td
|
…
|
|
|
RISCVScheduleV.td
|
[RISCV] Add scheduler class to PseudoReadVLENB.
|
2022-08-02 09:38:32 -07:00 |
|
RISCVSubtarget.cpp
|
[RISCV] Enable fixed length vectors and loop vectorization with same
|
2022-08-26 14:45:23 -07:00 |
|
RISCVSubtarget.h
|
[RISCV][MC] Add minimal support for Ztso extension
|
2022-09-07 09:30:57 -07:00 |
|
RISCVSystemOperands.td
|
…
|
|
|
RISCVTargetMachine.cpp
|
[RISCV] Add the GlobalMerge pass (disabled by default)
|
2022-09-08 18:40:38 -07:00 |
|
RISCVTargetMachine.h
|
[llvm] Remove redundaunt virtual specifiers (NFC)
|
2022-07-24 21:50:35 -07:00 |
|
RISCVTargetObjectFile.cpp
|
…
|
|
|
RISCVTargetObjectFile.h
|
…
|
|
|
RISCVTargetTransformInfo.cpp
|
Fix a -Wswitch warning.
|
2022-09-13 08:57:43 +02:00 |
|
RISCVTargetTransformInfo.h
|
[RISCV] Add RecurKind::FMulAdd to isLegalToVectorizeReduction for scalable vectors.
|
2022-09-08 12:34:59 -07:00 |
7ed68182d7