128 lines
3.6 KiB
LLVM
128 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBT
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declare i32 @llvm.riscv.fsl.i32(i32, i32, i32)
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define i32 @fsl_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; RV64ZBT-LABEL: fsl_i32:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fslw a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 %c)
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ret i32 %1
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}
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define i32 @fsl_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
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; RV64ZBT-LABEL: fsl_i32_demandedbits:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: andi a1, a1, 31
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; RV64ZBT-NEXT: fslw a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%bmask = and i32 %b, 95
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%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %bmask, i32 %c)
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ret i32 %1
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}
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declare i32 @llvm.riscv.fsr.i32(i32, i32, i32)
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define i32 @fsr_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; RV64ZBT-LABEL: fsr_i32:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsrw a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 %c)
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ret i32 %1
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}
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define i32 @fsr_i32_demandedbits(i32 %a, i32 %b, i32 %c) nounwind {
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; RV64ZBT-LABEL: fsr_i32_demandedbits:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: andi a1, a1, 31
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; RV64ZBT-NEXT: fsrw a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%bmask = and i32 %b, 95
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%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %bmask, i32 %c)
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ret i32 %1
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}
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define i32 @fsli_i32(i32 %a, i32 %b) nounwind {
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; RV64ZBT-LABEL: fsli_i32:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
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; RV64ZBT-NEXT: ret
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%1 = call i32 @llvm.riscv.fsl.i32(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
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; RV64ZBT-LABEL: fsri_i32:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsriw a0, a0, a1, 15
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; RV64ZBT-NEXT: ret
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%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 15)
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ret i32 %1
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}
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declare i64 @llvm.riscv.fsl.i64(i64, i64, i64)
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define i64 @fsl_i64(i64 %a, i64 %b, i64 %c) nounwind {
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; RV64ZBT-LABEL: fsl_i64:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsl a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %b, i64 %c)
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ret i64 %1
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}
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define i64 @fsl_i64_demandedbits(i64 %a, i64 %b, i64 %c) nounwind {
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; RV64ZBT-LABEL: fsl_i64_demandedbits:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: andi a1, a1, 63
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; RV64ZBT-NEXT: fsl a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%bmask = and i64 %b, 191
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%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %bmask, i64 %c)
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ret i64 %1
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}
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declare i64 @llvm.riscv.fsr.i64(i64, i64, i64)
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define i64 @fsr_i64(i64 %a, i64 %b, i64 %c) nounwind {
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; RV64ZBT-LABEL: fsr_i64:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsr a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %b, i64 %c)
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ret i64 %1
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}
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define i64 @fsr_i64_demandedbits(i64 %a, i64 %b, i64 %c) nounwind {
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; RV64ZBT-LABEL: fsr_i64_demandedbits:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: andi a1, a1, 63
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; RV64ZBT-NEXT: fsr a0, a0, a1, a2
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; RV64ZBT-NEXT: ret
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%bmask = and i64 %b, 191
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%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %bmask, i64 %c)
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ret i64 %1
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}
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define i64 @fsli_i64(i64 %a, i64 %b) nounwind {
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; RV64ZBT-LABEL: fsli_i64:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsri a0, a1, a0, 49
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; RV64ZBT-NEXT: ret
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%1 = call i64 @llvm.riscv.fsl.i64(i64 %a, i64 %b, i64 15)
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ret i64 %1
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}
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define i64 @fsri_i64(i64 %a, i64 %b) nounwind {
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; RV64ZBT-LABEL: fsri_i64:
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; RV64ZBT: # %bb.0:
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; RV64ZBT-NEXT: fsri a0, a0, a1, 5
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; RV64ZBT-NEXT: ret
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%1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %b, i64 5)
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ret i64 %1
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}
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