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AArch64
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Fix RUN line in AArch64/speculation-hardening.ll
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2020-04-02 09:42:15 +01:00 |
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AMDGPU
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AMDGPU: Add some tests for exotic denormal mode combinations
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2020-04-02 17:17:12 -04:00 |
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ARC
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ARM
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[ARM] Fix qdadd operand order
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2020-03-31 10:11:36 +01:00 |
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AVR
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[AVR] Generalize the previous interrupt bugfix to signal handlers too
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2020-03-31 19:33:34 +13:00 |
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BPF
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[BPF] support 128bit int explicitly in layout spec
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2020-03-28 11:46:29 -07:00 |
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Generic
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[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
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2020-03-26 14:10:20 -07:00 |
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Hexagon
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Revert "Include static prof data when collecting loop BBs"
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2020-03-24 09:41:16 -07:00 |
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Inputs
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Lanai
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MIR
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AMDGPU: Assume f32 denormals are enabled by default
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2020-04-02 17:17:12 -04:00 |
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MSP430
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Mips
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[Mips] Make MipsBranchExpansion aware of BBIT family of branch
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2020-03-31 09:20:51 +02:00 |
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NVPTX
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[DAGCombiner] Require ninf for sqrt recip estimation
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2020-04-01 16:23:43 +08:00 |
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PowerPC
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[NFC][PowerPC] Using update_llc_test_checks.py to update atomics-regression.ll
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2020-04-02 12:47:35 +00:00 |
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RISCV
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[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
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2020-04-01 15:51:26 +01:00 |
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SPARC
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[Sparc] Fix incorrect operand for matching CMPri pattern
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2020-03-02 11:36:32 +08:00 |
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SystemZ
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[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
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2020-04-02 14:57:46 +02:00 |
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Thumb
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[DAGCombine] Skip PostInc combine with later users
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2020-03-23 08:39:53 +00:00 |
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Thumb2
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[ARM] MVE VMULL patterns
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2020-04-02 10:57:40 +01:00 |
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VE
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[VE] Target-specific bit size for sjljehprepare
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2020-03-10 17:51:16 +01:00 |
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WebAssembly
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[WebAssembly] EmscriptenEHSjLj: Mark __invoke_ functions as imported
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2020-04-01 16:33:33 -07:00 |
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WinCFGuard
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WinEH
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X86
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[X86] Enable combineExtSetcc for vectors larger than 256 bits when we've disabled 512 bit vectors.
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2020-04-02 12:44:27 -07:00 |
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XCore
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[XCore] Add instruction pattern for bitrev
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2020-02-21 09:28:49 +08:00 |
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