582 lines
20 KiB
C++
582 lines
20 KiB
C++
//===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the checking of insns inside a bundle according to the
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// packet constraint rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCChecker.h"
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#include "HexagonBaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static cl::opt<bool> RelaxNVChecks("relax-nv-checks", cl::init(false),
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cl::ZeroOrMore, cl::Hidden, cl::desc("Relax checks of new-value validity"));
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const HexagonMCChecker::PredSense
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HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
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void HexagonMCChecker::init() {
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// Initialize read-only registers set.
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ReadOnly.insert(Hexagon::PC);
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// Figure out the loop-registers definitions.
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if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
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Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
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Defs[Hexagon::LC0].insert(Unconditional);
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}
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if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
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Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
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Defs[Hexagon::LC1].insert(Unconditional);
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}
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if (HexagonMCInstrInfo::isBundle(MCB))
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// Unfurl a bundle.
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for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
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init(*I.getInst());
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}
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else
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init(MCB);
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}
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void HexagonMCChecker::init(MCInst const& MCI) {
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const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
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unsigned PredReg = Hexagon::NoRegister;
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bool isTrue = false;
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// Get used registers.
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for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
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if (MCI.getOperand(i).isReg()) {
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unsigned R = MCI.getOperand(i).getReg();
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if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
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// Note an used predicate register.
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PredReg = R;
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isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
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// Note use of new predicate register.
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if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
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NewPreds.insert(PredReg);
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}
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else
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// Note register use. Super-registers are not tracked directly,
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// but their components.
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for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
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SRI.isValid();
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++SRI)
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if (!MCSubRegIterator(*SRI, &RI).isValid())
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// Skip super-registers used indirectly.
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Uses.insert(*SRI);
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}
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// Get implicit register definitions.
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if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
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for (; *ImpDef; ++ImpDef) {
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unsigned R = *ImpDef;
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if (Hexagon::R31 != R && MCID.isCall())
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// Any register other than the LR and the PC are actually volatile ones
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// as defined by the ABI, not modified implicitly by the call insn.
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continue;
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if (Hexagon::PC == R)
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// Branches are the only insns that can change the PC,
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// otherwise a read-only register.
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continue;
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if (Hexagon::USR_OVF == R)
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// Many insns change the USR implicitly, but only one or another flag.
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// The instruction table models the USR.OVF flag, which can be implicitly
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// modified more than once, but cannot be modified in the same packet
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// with an instruction that modifies is explicitly. Deal with such situ-
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// ations individually.
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SoftDefs.insert(R);
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else if (isPredicateRegister(R) &&
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HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
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// Include implicit late predicates.
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LatePreds.insert(R);
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else
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Defs[R].insert(PredSense(PredReg, isTrue));
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}
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// Figure out explicit register definitions.
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for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
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unsigned R = MCI.getOperand(i).getReg(),
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S = Hexagon::NoRegister;
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// Note register definitions, direct ones as well as indirect side-effects.
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// Super-registers are not tracked directly, but their components.
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for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
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SRI.isValid();
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++SRI) {
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if (MCSubRegIterator(*SRI, &RI).isValid())
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// Skip super-registers defined indirectly.
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continue;
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if (R == *SRI) {
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if (S == R)
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// Avoid scoring the defined register multiple times.
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continue;
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else
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// Note that the defined register has already been scored.
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S = R;
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}
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if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
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// P3:0 is a special case, since multiple predicate register definitions
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// in a packet is allowed as the equivalent of their logical "and".
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// Only an explicit definition of P3:0 is noted as such; if a
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// side-effect, then note as a soft definition.
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SoftDefs.insert(*SRI);
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else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI))
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// Some insns produce predicates too late to be used in the same packet.
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LatePreds.insert(*SRI);
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else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD)
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// Current loads should be used in the same packet.
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// TODO: relies on the impossibility of a current and a temporary loads
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// in the same packet.
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CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));
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else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD)
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// Temporary loads should be used in the same packet, but don't commit
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// results, so it should be disregarded if another insn changes the same
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// register.
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// TODO: relies on the impossibility of a current and a temporary loads
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// in the same packet.
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TmpDefs.insert(*SRI);
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else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) )
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// vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
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// destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
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Uses.insert(*SRI);
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else
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Defs[*SRI].insert(PredSense(PredReg, isTrue));
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}
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}
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// Figure out register definitions that produce new values.
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if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) {
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unsigned R = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
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if (HexagonMCInstrInfo::isCompound(MCII, MCI))
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compoundRegisterMap(R); // Compound insns have a limited register range.
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for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
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SRI.isValid();
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++SRI)
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if (!MCSubRegIterator(*SRI, &RI).isValid())
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// No super-registers defined indirectly.
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NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
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HexagonMCInstrInfo::isFloat(MCII, MCI)));
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// For fairly unique 2-dot-new producers, example:
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// vdeal(V1, V9, R0) V1.new and V9.new can be used by consumers.
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if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) {
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unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg();
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for(MCRegAliasIterator SRI(R2, &RI, !MCSubRegIterator(R2, &RI).isValid());
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SRI.isValid();
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++SRI)
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if (!MCSubRegIterator(*SRI, &RI).isValid())
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NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
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HexagonMCInstrInfo::isFloat(MCII, MCI)));
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}
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}
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// Figure out definitions of new predicate registers.
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if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
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for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
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if (MCI.getOperand(i).isReg()) {
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unsigned P = MCI.getOperand(i).getReg();
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if (isPredicateRegister(P))
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NewPreds.insert(P);
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}
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// Figure out uses of new values.
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if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) {
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unsigned N = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
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if (!MCSubRegIterator(N, &RI).isValid()) {
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// Super-registers cannot use new values.
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if (MCID.isBranch())
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NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV);
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else
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NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
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}
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}
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}
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HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx,
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MCRegisterInfo const &ri)
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: MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),
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bLoadErrInfo(false) {
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init();
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}
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bool HexagonMCChecker::check() {
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bool chkB = checkBranches();
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bool chkP = checkPredicates();
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bool chkNV = checkNewValues();
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bool chkR = checkRegisters();
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bool chkS = checkSolo();
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bool chkSh = checkShuffle();
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bool chkSl = checkSlots();
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bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;
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return chk;
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}
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bool HexagonMCChecker::checkSlots()
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{
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unsigned slotsUsed = 0;
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for (auto HMI: HexagonMCInstrInfo::bundleInstructions(MCBDX)) {
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MCInst const& MCI = *HMI.getInst();
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if (HexagonMCInstrInfo::isImmext(MCI))
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continue;
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if (HexagonMCInstrInfo::isDuplex(MCII, MCI))
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slotsUsed += 2;
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else
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++slotsUsed;
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}
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if (slotsUsed > HEXAGON_PACKET_SIZE) {
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HexagonMCErrInfo errInfo;
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NOSLOTS);
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addErrInfo(errInfo);
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return false;
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}
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return true;
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}
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// Check legal use of branches.
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bool HexagonMCChecker::checkBranches() {
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HexagonMCErrInfo errInfo;
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if (HexagonMCInstrInfo::isBundle(MCB)) {
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bool hasConditional = false;
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unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0,
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NewValueBranches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,
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Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE;
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for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset;
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i < MCB.size(); ++i) {
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MCInst const &MCI = *MCB.begin()[i].getInst();
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if (HexagonMCInstrInfo::isImmext(MCI))
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continue;
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if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() ||
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HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) {
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++Branches;
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if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() &&
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HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
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++NewIndirectBranches;
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if (HexagonMCInstrInfo::isNewValue(MCII, MCI))
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++NewValueBranches;
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if (HexagonMCInstrInfo::isPredicated(MCII, MCI) ||
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HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) {
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hasConditional = true;
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Conditional = i; // Record the position of the conditional branch.
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} else {
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Unconditional = i; // Record the position of the unconditional branch.
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}
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}
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if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() &&
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HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad())
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++Returns;
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}
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if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too?
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if (HexagonMCInstrInfo::isInnerLoop(MCB) ||
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HexagonMCInstrInfo::isOuterLoop(MCB)) {
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// Error out if there's any branch in a loop-end packet.
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_ENDLOOP, Hexagon::PC);
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addErrInfo(errInfo);
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return false;
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}
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if (Branches > 1)
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if (!hasConditional || Conditional > Unconditional) {
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// Error out if more than one unconditional branch or
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// the conditional branch appears after the unconditional one.
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_BRANCHES);
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addErrInfo(errInfo);
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return false;
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}
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}
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return true;
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}
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// Check legal use of predicate registers.
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bool HexagonMCChecker::checkPredicates() {
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HexagonMCErrInfo errInfo;
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// Check for proper use of new predicate registers.
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for (const auto& I : NewPreds) {
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unsigned P = I;
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if (!Defs.count(P) || LatePreds.count(P)) {
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// Error out if the new predicate register is not defined,
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// or defined "late"
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// (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWP, P);
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addErrInfo(errInfo);
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return false;
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}
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}
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// Check for proper use of auto-anded of predicate registers.
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for (const auto& I : LatePreds) {
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unsigned P = I;
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if (LatePreds.count(P) > 1 || Defs.count(P)) {
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// Error out if predicate register defined "late" multiple times or
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// defined late and regularly defined
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// (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, P);
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addErrInfo(errInfo);
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return false;
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}
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}
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return true;
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}
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// Check legal use of new values.
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bool HexagonMCChecker::checkNewValues() {
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HexagonMCErrInfo errInfo;
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memset(&errInfo, 0, sizeof(errInfo));
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for (auto& I : NewUses) {
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unsigned R = I.first;
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NewSense &US = I.second;
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if (!hasValidNewValueDef(US, NewDefs[R])) {
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWV, R);
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addErrInfo(errInfo);
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return false;
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}
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}
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return true;
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}
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// Check for legal register uses and definitions.
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bool HexagonMCChecker::checkRegisters() {
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HexagonMCErrInfo errInfo;
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// Check for proper register definitions.
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for (const auto& I : Defs) {
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unsigned R = I.first;
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if (ReadOnly.count(R)) {
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// Error out for definitions of read-only registers.
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_READONLY, R);
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addErrInfo(errInfo);
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return false;
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}
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if (isLoopRegister(R) && Defs.count(R) > 1 &&
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(HexagonMCInstrInfo::isInnerLoop(MCB) ||
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HexagonMCInstrInfo::isOuterLoop(MCB))) {
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// Error out for definitions of loop registers at the end of a loop.
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_LOOP, R);
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addErrInfo(errInfo);
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return false;
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}
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if (SoftDefs.count(R)) {
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// Error out for explicit changes to registers also weakly defined
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// (e.g., "{ usr = r0; r0 = sfadd(...) }").
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unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
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unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);
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addErrInfo(errInfo);
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return false;
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}
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if (!isPredicateRegister(R) && Defs[R].size() > 1) {
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// Check for multiple register definitions.
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PredSet &PM = Defs[R];
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// Check for multiple unconditional register definitions.
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if (PM.count(Unconditional)) {
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// Error out on an unconditional change when there are any other
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// changes, conditional or not.
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unsigned UsrR = Hexagon::USR;
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unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);
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addErrInfo(errInfo);
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return false;
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}
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// Check for multiple conditional register definitions.
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for (const auto& J : PM) {
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PredSense P = J;
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// Check for multiple uses of the same condition.
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if (PM.count(P) > 1) {
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// Error out on conditional changes based on the same predicate
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// (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);
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addErrInfo(errInfo);
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return false;
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}
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// Check for the use of the complementary condition.
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P.second = !P.second;
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if (PM.count(P) && PM.size() > 2) {
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// Error out on conditional changes based on the same predicate
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// multiple times
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// (e.g., "{ if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =... }").
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errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);
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addErrInfo(errInfo);
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return false;
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}
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}
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}
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}
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// Check for use of current definitions.
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for (const auto& I : CurDefs) {
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unsigned R = I;
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if (!Uses.count(R)) {
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// Warn on an unused current definition.
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errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_CURRENT, R);
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addErrInfo(errInfo);
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return true;
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}
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}
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// Check for use of temporary definitions.
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for (const auto& I : TmpDefs) {
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unsigned R = I;
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if (!Uses.count(R)) {
|
|
// special case for vhist
|
|
bool vHistFound = false;
|
|
for (auto const&HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
|
|
if(llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) == HexagonII::TypeCVI_HIST) {
|
|
vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
|
|
break;
|
|
}
|
|
}
|
|
// Warn on an unused temporary definition.
|
|
if (vHistFound == false) {
|
|
errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_TEMPORARY, R);
|
|
addErrInfo(errInfo);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Check for legal use of solo insns.
|
|
bool HexagonMCChecker::checkSolo() {
|
|
HexagonMCErrInfo errInfo;
|
|
if (HexagonMCInstrInfo::isBundle(MCB) &&
|
|
HexagonMCInstrInfo::bundleSize(MCB) > 1) {
|
|
for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
|
|
if (llvm::HexagonMCInstrInfo::isSolo(MCII, *I.getInst())) {
|
|
errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SOLO);
|
|
addErrInfo(errInfo);
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool HexagonMCChecker::checkShuffle() {
|
|
HexagonMCErrInfo errInfo;
|
|
// Branch info is lost when duplexing. The unduplexed insns must be
|
|
// checked and only branch errors matter for this case.
|
|
HexagonMCShuffler MCS(MCII, STI, MCB);
|
|
if (!MCS.check()) {
|
|
if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR_BRANCHES) {
|
|
errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
|
|
errInfo.setShuffleError(MCS.getError());
|
|
addErrInfo(errInfo);
|
|
return false;
|
|
}
|
|
}
|
|
HexagonMCShuffler MCSDX(MCII, STI, MCBDX);
|
|
if (!MCSDX.check()) {
|
|
errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
|
|
errInfo.setShuffleError(MCSDX.getError());
|
|
addErrInfo(errInfo);
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void HexagonMCChecker::compoundRegisterMap(unsigned& Register) {
|
|
switch (Register) {
|
|
default:
|
|
break;
|
|
case Hexagon::R15:
|
|
Register = Hexagon::R23;
|
|
break;
|
|
case Hexagon::R14:
|
|
Register = Hexagon::R22;
|
|
break;
|
|
case Hexagon::R13:
|
|
Register = Hexagon::R21;
|
|
break;
|
|
case Hexagon::R12:
|
|
Register = Hexagon::R20;
|
|
break;
|
|
case Hexagon::R11:
|
|
Register = Hexagon::R19;
|
|
break;
|
|
case Hexagon::R10:
|
|
Register = Hexagon::R18;
|
|
break;
|
|
case Hexagon::R9:
|
|
Register = Hexagon::R17;
|
|
break;
|
|
case Hexagon::R8:
|
|
Register = Hexagon::R16;
|
|
break;
|
|
}
|
|
}
|
|
|
|
bool HexagonMCChecker::hasValidNewValueDef(const NewSense &Use,
|
|
const NewSenseList &Defs) const {
|
|
bool Strict = !RelaxNVChecks;
|
|
|
|
for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
|
|
const NewSense &Def = Defs[i];
|
|
// NVJ cannot use a new FP value [7.6.1]
|
|
if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0))
|
|
continue;
|
|
// If the definition was not predicated, then it does not matter if
|
|
// the use is.
|
|
if (Def.PredReg == 0)
|
|
return true;
|
|
// With the strict checks, both the definition and the use must be
|
|
// predicated on the same register and condition.
|
|
if (Strict) {
|
|
if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond)
|
|
return true;
|
|
} else {
|
|
// With the relaxed checks, if the definition was predicated, the only
|
|
// detectable violation is if the use is predicated on the opposing
|
|
// condition, otherwise, it's ok.
|
|
if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond)
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|