742 lines
26 KiB
C++
742 lines
26 KiB
C++
//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonFixupKinds.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "mccodeemitter"
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using namespace llvm;
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using namespace Hexagon;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCContext &aMCT)
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: MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
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Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
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uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
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MCInst const &MCB,
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MCInst const &MCI) const {
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bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
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if (Instruction == 0) {
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if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
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assert(!Duplex);
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assert(Instruction != Last);
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return HexagonII::INST_PARSE_LOOP_END;
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}
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}
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if (Instruction == 1) {
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if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
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assert(!Duplex);
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assert(Instruction != Last);
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return HexagonII::INST_PARSE_LOOP_END;
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}
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}
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if (Duplex) {
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assert(Instruction == Last);
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return HexagonII::INST_PARSE_DUPLEX;
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}
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if(Instruction == Last)
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return HexagonII::INST_PARSE_PACKET_END;
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return HexagonII::INST_PARSE_NOT_END;
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}
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void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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MCInst &HMB = const_cast<MCInst &>(MI);
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assert(HexagonMCInstrInfo::isBundle(HMB));
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DEBUG(dbgs() << "Encoding bundle\n";);
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*Addend = 0;
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*Extended = false;
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*CurrentBundle = &MI;
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size_t Instruction = 0;
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size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
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for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
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MCInst &HMI = const_cast<MCInst &>(*I.getInst());
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EncodeSingleInstruction(HMI, OS, Fixups, STI,
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parseBits(Instruction, Last, HMB, HMI),
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Instruction);
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*Extended = HexagonMCInstrInfo::isImmext(HMI);
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*Addend += HEXAGON_INSTR_SIZE;
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++Instruction;
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}
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return;
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}
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/// EncodeSingleInstruction - Emit a single
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void HexagonMCCodeEmitter::EncodeSingleInstruction(
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const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
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MCInst HMB = MI;
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assert(!HexagonMCInstrInfo::isBundle(HMB));
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uint64_t Binary;
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// Compound instructions are limited to using registers 0-7 and 16-23
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// and here we make a map 16-23 to 8-15 so they can be correctly encoded.
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static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10,
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Hexagon::R11, Hexagon::R12, Hexagon::R13,
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Hexagon::R14, Hexagon::R15};
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// Pseudo instructions don't get encoded and shouldn't be here
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// in the first place!
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assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
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"pseudo-instruction found");
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DEBUG(dbgs() << "Encoding insn"
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" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
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"\n");
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if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
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for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
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if (HMB.getOperand(i).isReg()) {
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unsigned Reg =
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MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
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if ((Reg <= 23) && (Reg >= 16))
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HMB.getOperand(i).setReg(RegMap[Reg - 16]);
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}
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}
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if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
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// Calculate the new value distance to the associated producer
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MCOperand &MCO =
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HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
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unsigned SOffset = 0;
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unsigned Register = MCO.getReg();
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unsigned Register1;
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auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
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auto i = Instructions.begin() + Index - 1;
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for (;; --i) {
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assert(i != Instructions.begin() - 1 && "Couldn't find producer");
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MCInst const &Inst = *i->getInst();
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if (HexagonMCInstrInfo::isImmext(Inst))
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continue;
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++SOffset;
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Register1 =
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HexagonMCInstrInfo::hasNewValue(MCII, Inst)
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? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
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: static_cast<unsigned>(Hexagon::NoRegister);
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if (Register != Register1)
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// This isn't the register we're looking for
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continue;
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if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
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// Producer is unpredicated
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break;
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assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
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"Unpredicated consumer depending on predicated producer");
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if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
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HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
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// Producer predicate sense matched ours
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break;
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}
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// Hexagon PRM 10.11 Construct Nt from distance
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unsigned Offset = SOffset;
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Offset <<= 1;
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MCO.setReg(Offset + Hexagon::R0);
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}
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Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
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// Check for unimplemented instructions. Immediate extenders
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// are encoded as zero, so they need to be accounted for.
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if ((!Binary) &&
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((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
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(HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
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(HMB.getOpcode() != A4_ext_g))) {
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// Use a A2_nop for unimplemented instructions.
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DEBUG(dbgs() << "Unimplemented inst: "
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" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
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"\n");
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llvm_unreachable("Unimplemented Instruction");
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}
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Binary |= Parse;
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// if we need to emit a duplexed instruction
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if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
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HMB.getOpcode() <= Hexagon::DuplexIClassF) {
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assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
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"Emitting duplex without duplex parse bits");
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unsigned dupIClass;
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switch (HMB.getOpcode()) {
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case Hexagon::DuplexIClass0:
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dupIClass = 0;
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break;
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case Hexagon::DuplexIClass1:
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dupIClass = 1;
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break;
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case Hexagon::DuplexIClass2:
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dupIClass = 2;
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break;
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case Hexagon::DuplexIClass3:
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dupIClass = 3;
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break;
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case Hexagon::DuplexIClass4:
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dupIClass = 4;
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break;
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case Hexagon::DuplexIClass5:
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dupIClass = 5;
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break;
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case Hexagon::DuplexIClass6:
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dupIClass = 6;
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break;
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case Hexagon::DuplexIClass7:
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dupIClass = 7;
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break;
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case Hexagon::DuplexIClass8:
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dupIClass = 8;
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break;
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case Hexagon::DuplexIClass9:
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dupIClass = 9;
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break;
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case Hexagon::DuplexIClassA:
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dupIClass = 10;
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break;
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case Hexagon::DuplexIClassB:
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dupIClass = 11;
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break;
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case Hexagon::DuplexIClassC:
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dupIClass = 12;
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break;
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case Hexagon::DuplexIClassD:
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dupIClass = 13;
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break;
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case Hexagon::DuplexIClassE:
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dupIClass = 14;
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break;
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case Hexagon::DuplexIClassF:
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dupIClass = 15;
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break;
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default:
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llvm_unreachable("Unimplemented DuplexIClass");
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break;
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}
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// 29 is the bit position.
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// 0b1110 =0xE bits are masked off and down shifted by 1 bit.
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// Last bit is moved to bit position 13
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Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
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const MCInst *subInst0 = HMB.getOperand(0).getInst();
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const MCInst *subInst1 = HMB.getOperand(1).getInst();
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// get subinstruction slot 0
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unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
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// get subinstruction slot 1
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unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
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Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
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}
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support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
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++MCNumEmitted;
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}
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static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
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const MCOperand &MO,
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const MCSymbolRefExpr::VariantKind kind) {
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
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unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
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if (insnType == HexagonII::TypePREFIX) {
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switch (kind) {
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case llvm::MCSymbolRefExpr::VK_GOTOFF:
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return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
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case llvm::MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_32_6_X;
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case llvm::MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_32_6_X;
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case llvm::MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
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case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
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case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_32_6_X;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
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default:
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if (MCID.isBranch())
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return Hexagon::fixup_Hexagon_B32_PCREL_X;
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else
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return Hexagon::fixup_Hexagon_32_6_X;
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}
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} else if (MCID.isBranch())
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return (Hexagon::fixup_Hexagon_B13_PCREL);
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switch (MCID.getOpcode()) {
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case Hexagon::HI:
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case Hexagon::A2_tfrih:
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switch (kind) {
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case llvm::MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_HI16;
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case llvm::MCSymbolRefExpr::VK_GOTOFF:
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return Hexagon::fixup_Hexagon_GOTREL_HI16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_HI16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_HI16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_HI16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_HI16;
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case llvm::MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_HI16;
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case llvm::MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_HI16;
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default:
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return Hexagon::fixup_Hexagon_HI16;
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}
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case Hexagon::LO:
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case Hexagon::A2_tfril:
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switch (kind) {
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case llvm::MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_LO16;
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case llvm::MCSymbolRefExpr::VK_GOTOFF:
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return Hexagon::fixup_Hexagon_GOTREL_LO16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_LO16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_LO16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_LO16;
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case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_LO16;
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case llvm::MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_LO16;
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case llvm::MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_LO16;
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default:
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return Hexagon::fixup_Hexagon_LO16;
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}
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// The only relocs left should be GP relative:
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default:
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if (MCID.mayStore() || MCID.mayLoad()) {
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for (const MCPhysReg *ImpUses = MCID.getImplicitUses();
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ImpUses && *ImpUses; ++ImpUses) {
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if (*ImpUses != Hexagon::GP)
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continue;
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switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
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case HexagonII::MemAccessSize::ByteAccess:
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return fixup_Hexagon_GPREL16_0;
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case HexagonII::MemAccessSize::HalfWordAccess:
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return fixup_Hexagon_GPREL16_1;
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case HexagonII::MemAccessSize::WordAccess:
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return fixup_Hexagon_GPREL16_2;
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case HexagonII::MemAccessSize::DoubleWordAccess:
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return fixup_Hexagon_GPREL16_3;
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default:
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llvm_unreachable("unhandled fixup");
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}
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}
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} else
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llvm_unreachable("unhandled fixup");
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}
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return LastTargetFixupKind;
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}
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namespace llvm {
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extern const MCInstrDesc HexagonInsts[];
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}
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namespace {
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bool isPCRel (unsigned Kind) {
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switch(Kind){
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case fixup_Hexagon_B22_PCREL:
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case fixup_Hexagon_B15_PCREL:
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case fixup_Hexagon_B7_PCREL:
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case fixup_Hexagon_B13_PCREL:
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case fixup_Hexagon_B9_PCREL:
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case fixup_Hexagon_B32_PCREL_X:
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case fixup_Hexagon_B22_PCREL_X:
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case fixup_Hexagon_B15_PCREL_X:
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case fixup_Hexagon_B13_PCREL_X:
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case fixup_Hexagon_B9_PCREL_X:
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case fixup_Hexagon_B7_PCREL_X:
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case fixup_Hexagon_32_PCREL:
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case fixup_Hexagon_PLT_B22_PCREL:
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case fixup_Hexagon_GD_PLT_B22_PCREL:
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case fixup_Hexagon_LD_PLT_B22_PCREL:
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case fixup_Hexagon_6_PCREL_X:
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return true;
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default:
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return false;
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}
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}
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}
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unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
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const MCOperand &MO,
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const MCExpr *ME,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const
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{
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int64_t Res;
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if (ME->evaluateAsAbsolute(Res))
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return Res;
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MCExpr::ExprKind MK = ME->getKind();
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if (MK == MCExpr::Constant) {
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return cast<MCConstantExpr>(ME)->getValue();
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}
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if (MK == MCExpr::Binary) {
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getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
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getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
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return 0;
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}
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assert(MK == MCExpr::SymbolRef);
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Hexagon::Fixups FixupKind =
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Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
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const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
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unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
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HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
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const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
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DEBUG(dbgs() << "----------------------------------------\n");
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DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
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<< "\n");
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DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
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DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
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DEBUG(dbgs() << "Addend: " << *Addend << "\n");
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DEBUG(dbgs() << "----------------------------------------\n");
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switch (bits) {
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default:
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DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
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break;
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case 32:
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switch (kind) {
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case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
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FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
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break;
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case llvm::MCSymbolRefExpr::VK_GOT:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
|
|
: Hexagon::fixup_Hexagon_GOT_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
|
|
: Hexagon::fixup_Hexagon_GOTREL_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
|
|
: Hexagon::fixup_Hexagon_GD_GOT_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
|
|
: Hexagon::fixup_Hexagon_LD_GOT_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
|
|
: Hexagon::fixup_Hexagon_IE_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
|
|
: Hexagon::fixup_Hexagon_IE_GOT_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
|
|
: Hexagon::fixup_Hexagon_TPREL_32;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
|
|
: Hexagon::fixup_Hexagon_DTPREL_32;
|
|
break;
|
|
default:
|
|
FixupKind =
|
|
*Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 22:
|
|
switch (kind) {
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
|
|
break;
|
|
default:
|
|
if (MCID.isBranch() || MCID.isCall()) {
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B22_PCREL;
|
|
} else {
|
|
errs() << "unrecognized relocation, bits: " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 16:
|
|
if (*Extended) {
|
|
switch (kind) {
|
|
default:
|
|
FixupKind = Hexagon::fixup_Hexagon_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
|
|
break;
|
|
}
|
|
} else
|
|
switch (kind) {
|
|
default:
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
if ((MCID.getOpcode() == Hexagon::HI) ||
|
|
(MCID.getOpcode() == Hexagon::LO_H))
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
|
|
else
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LO16:
|
|
FixupKind = Hexagon::fixup_Hexagon_LO16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_HI16:
|
|
FixupKind = Hexagon::fixup_Hexagon_HI16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 15:
|
|
if (MCID.isBranch() || MCID.isCall())
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B15_PCREL;
|
|
break;
|
|
|
|
case 13:
|
|
if (MCID.isBranch())
|
|
FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 12:
|
|
if (*Extended)
|
|
switch (kind) {
|
|
default:
|
|
FixupKind = Hexagon::fixup_Hexagon_12_X;
|
|
break;
|
|
// There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
|
|
case llvm::MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
|
|
break;
|
|
}
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 11:
|
|
if (*Extended)
|
|
switch (kind) {
|
|
default:
|
|
FixupKind = Hexagon::fixup_Hexagon_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
|
|
break;
|
|
}
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 10:
|
|
if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_10_X;
|
|
break;
|
|
|
|
case 9:
|
|
if (MCID.isBranch() ||
|
|
(llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B9_PCREL;
|
|
else if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_9_X;
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 8:
|
|
if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_8_X;
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 7:
|
|
if (MCID.isBranch() ||
|
|
(llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B7_PCREL;
|
|
else if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_7_X;
|
|
else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 6:
|
|
if (*Extended) {
|
|
switch (kind) {
|
|
default:
|
|
FixupKind = Hexagon::fixup_Hexagon_6_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
|
|
break;
|
|
// This is part of an extender, GOT_11 is a
|
|
// Word32_U6 unsigned/truncated reloc.
|
|
case llvm::MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
|
|
break;
|
|
case llvm::MCSymbolRefExpr::VK_GOTOFF:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
|
|
break;
|
|
}
|
|
} else {
|
|
errs() << "unrecognized relocation, bits " << bits << "\n";
|
|
errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
|
|
}
|
|
break;
|
|
|
|
case 0:
|
|
FixupKind = getFixupNoBits(MCII, MI, MO, kind);
|
|
break;
|
|
}
|
|
|
|
MCExpr const *FixupExpression = (*Addend > 0 && isPCRel(FixupKind)) ?
|
|
MCBinaryExpr::createAdd(MO.getExpr(),
|
|
MCConstantExpr::create(*Addend, MCT), MCT) :
|
|
MO.getExpr();
|
|
|
|
MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
|
|
MCFixupKind(FixupKind), MI.getLoc());
|
|
Fixups.push_back(fixup);
|
|
// All of the information is in the fixup.
|
|
return (0);
|
|
}
|
|
|
|
unsigned
|
|
HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
MCSubtargetInfo const &STI) const {
|
|
if (MO.isReg())
|
|
return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
|
|
if (MO.isImm())
|
|
return static_cast<unsigned>(MO.getImm());
|
|
|
|
// MO must be an ME.
|
|
assert(MO.isExpr());
|
|
return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
|
|
}
|
|
|
|
MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
|
|
MCRegisterInfo const &MRI,
|
|
MCContext &MCT) {
|
|
return new HexagonMCCodeEmitter(MII, MCT);
|
|
}
|
|
|
|
#include "HexagonGenMCCodeEmitter.inc"
|