77 lines
2.5 KiB
LLVM
77 lines
2.5 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; FUNC-LABEL: {{^}}u32_mad24:
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; EG: MULADD_UINT24
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; SI: v_mad_u32_u24
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define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = lshr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = lshr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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%3 = add i32 %2, %c
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}i16_mad24:
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; The order of A and B does not matter.
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; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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; The result must be sign-extended
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; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG: 16
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; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16
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define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
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entry:
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%0 = mul i16 %a, %b
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%1 = add i16 %0, %c
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%2 = sext i16 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}i8_mad24:
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; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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; The result must be sign-extended
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; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG: 8
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; SI: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
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define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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entry:
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%0 = mul i8 %a, %b
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%1 = add i8 %0, %c
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%2 = sext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; This tests for a bug where the mad_u24 pattern matcher would call
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; SimplifyDemandedBits on the first operand of the mul instruction
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; assuming that the pattern would be matched to a 24-bit mad. This
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; led to some instructions being incorrectly erased when the entire
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; 24-bit mad pattern wasn't being matched.
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; Check that the select instruction is not deleted.
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; FUNC-LABEL: {{^}}i24_i32_i32_mad:
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; EG: CNDE_INT
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; SI: v_cndmask
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define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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entry:
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%0 = ashr i32 %a, 8
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%1 = icmp ne i32 %c, 0
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%2 = select i1 %1, i32 %0, i32 34
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%3 = mul i32 %2, %c
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%4 = add i32 %3, %d
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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