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llvm-project/llvm/test/MC/Disassembler/AMDGPU
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David Stuttard 70e8bc1bf3 [AMDGPU] Add intrinsics for tbuffer load and store 
Intrinsic already existed for llvm.SI.tbuffer.store

Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.*

Added CodeGen tests for the 2 new variants added.
Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr

Differential Revision: https://reviews.llvm.org/D30687

llvm-svn: 306031
 		2017-06-22 16:29:22 +00:00
..
aperture-regs.ll AMDGPU: Fix disassembly of aperture registers 2017-02-18 18:41:41 +00:00
dpp_vi.txt [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa 2016-12-22 11:30:48 +00:00
ds_vi.txt [AMDGPU][MC] Fix for Bug 28211 + LIT tests 2017-04-07 13:07:13 +00:00
exp_vi.txt [AMDGPU][MC] Fixed bugs in export instruction 2017-05-19 13:36:09 +00:00
flat_vi.txt AMDGPU: Remove tfe bit from flat instruction definitions 2017-05-11 17:38:33 +00:00
gfx8_dasm_all.txt [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests. 2017-06-19 15:55:02 +00:00
gfx9_dasm_all.txt [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failures 2017-06-21 16:00:54 +00:00
lit.local.cfg
…
literal16_vi.txt [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output 2017-05-10 13:00:28 +00:00
mac.txt AMDGPU: Fix crash when disassembling VOP3 mac 2017-04-10 17:58:06 +00:00
mov.txt
…
mtbuf_vi.txt [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
mubuf_vi.txt [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3. 2016-10-07 15:53:16 +00:00
nop.txt
…
sdwa_gfx9.txt [AMDGPU] SDWA: add disassembler support for GFX9 2017-05-26 15:52:00 +00:00
sdwa_vi.txt [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa 2016-12-22 11:30:48 +00:00
si-support.txt AMDGPU: Replace assert with report_fatal_error 2017-02-15 21:50:34 +00:00
smem_vi.txt [AMDGPU] Disassembler: fix s_buffer_store_dword instructions 2016-12-05 09:58:51 +00:00
smrd_vi.txt [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
sop1_vi.txt [AMDGPU][MC] Corrected src0 size for s_cbranch_join 2017-04-12 12:40:19 +00:00
sop2_vi.txt
…
sopc_vi.txt [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals 2017-05-19 14:27:52 +00:00
sopk_vi.txt
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sopp_vi.txt [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. 2016-05-06 17:48:48 +00:00
trap_vi.txt [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers. 2016-05-24 12:05:16 +00:00
vintrp.txt AMDGPU: Change vintrp printing 2016-12-14 16:36:12 +00:00
vop1.txt AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
vop1_gfx9.txt AMDGPU: Add definition for v_swap_b32 2017-02-28 21:09:04 +00:00
vop1_vi.txt
…
vop2_vi.txt [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64 2017-05-15 14:28:23 +00:00
vop3_vi.txt [AMDGPU][MC] Removed V_MQSAD_U16_U8 2017-05-15 12:37:03 +00:00
vopc_vi.txt
…