Matt Arsenault 1024b73ef5 AMDGPU: Split denormal mode tracking bits ... Prepare to accurately track the future denormal-fp-math attribute changes. The way to actually set these separately is not wired in yet. This is just a mechanical change, and mostly still assumes the input and output mode match. This should be refined for some cases. For example, fcanonicalize lowering should use the flushing variant if either input or output flushing is enabled		2020-02-04 10:44:21 -08:00
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expected-target-index-name.mir	[AMDGPU] Extend buffer intrinsics with swizzling	2019-10-02 17:22:36 +00:00
intrinsics.mir	…
invalid-target-index-operand.mir	[AMDGPU] Extend buffer intrinsics with swizzling	2019-10-02 17:22:36 +00:00
lit.local.cfg	…
llc-target-cpu-attr-from-cmdline-ir.mir	llc: Change behavior of -mcpu with existing attribute	2020-01-07 10:10:25 -05:00
llc-target-cpu-attr-from-cmdline.mir	llc/MIR: Fix setFunctionAttributes for MIR functions	2020-01-06 17:21:51 -05:00
load-store-opt-dlc.mir	[AMDGPU] Extend buffer intrinsics with swizzling	2019-10-02 17:22:36 +00:00
machine-function-info-no-ir.mir	AMDGPU: Split denormal mode tracking bits	2020-02-04 10:44:21 -08:00
machine-function-info-register-parse-error1.mir	…
machine-function-info-register-parse-error2.mir	…
machine-function-info.ll	AMDGPU: Split denormal mode tracking bits	2020-02-04 10:44:21 -08:00
mfi-frame-offset-reg-class.mir	…
mfi-parse-error-frame-offset-reg.mir	…
mfi-parse-error-scratch-rsrc-reg.mir	…
mfi-parse-error-scratch-wave-offset-reg.mir	…
mfi-parse-error-stack-ptr-offset-reg.mir	…
mfi-scratch-rsrc-reg-reg-class.mir	…
mfi-scratch-wave-offset-reg-class.mir	…
mfi-stack-ptr-offset-reg-class.mir	…
mir-canon-multi.mir	[MIRNamer]: Make the check lines in the test robust with regex.	2019-11-16 22:58:45 -08:00
mircanon-memoperands.mir	[llvm][MIRVRegNamerUtils] Adding hashing on memoperands.	2019-12-11 22:11:49 -05:00
parse-order-reserved-regs.mir	[AMDGPU] Extend buffer intrinsics with swizzling	2019-10-02 17:22:36 +00:00
stack-id.mir	Describe stack-id as an enum	2019-06-17 09:13:29 +00:00
syncscopes.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
target-flags.mir	AMDGPU: Prepare for explicit absolute relocations in code generation	2019-06-16 17:43:37 +00:00
target-index-operands.mir	[AMDGPU] Extend buffer intrinsics with swizzling	2019-10-02 17:22:36 +00:00